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CMX7163 qam modem ? datasheet advance information 7163 fi - 4.x qam modem features ? ? image? (fi) ? o 4/16/64 qam up to 96kbps in 25khz o different rate, robust fec choices o channel estimation and equalisation o fec and raw (uncoded) modes o two x frame sync detectors o automatic frame sync detect o formatted blocks for packet construction o rx carrier frequency and phase correction o receive signal quality measurement ? o tx and rx: direct connect to zero if transceiver o simple external rc filters o digital if filter reconfigures for multip le rf channel spacings (rx) o deviation control without manual trim (tx) o i/q trims ? o spi - like with register addressing o read/write 128 - byte fifos and data buffers streamline transfers and relax host service latency ? o four x 10 - bit dacs o autonomous ramdac sequencer o automatic support for dc calibration of cmx998 o four x 10 - bit adcs o adc averaging and trip on high/low watch modes o four x gpio o sequence gpio on tx or rx trigger o start tx on digital trigger input ? o for external slave devices e.g. rf transceiver and synthesiser o pass - through mode expands host c - bus/spi capacity ? ? ? applications ? o telemetry/scada/data modems o 6.25khz to 25khz rf channel spacing o compatible worldwide e.g. etsi, fcc, arib, etc. o fcc part 90 per new spectral efficiency requirements ? ? ? mobile data over fading channels cml microcircuits communication semiconductors modulation - specific function image? host c aux 4 x dac modulate r e g i s t e r s fifo configuration digital filters fec digital filters dacs adcs rf tx rf rx aux 2 x clk synth aux 4 x gpio 3 . 3 v external serial devices c - bus / spi master 3 . 3 v modem aux 4 x adc c - bus cmx 7163 qam modem
CMX7163 qam modem CMX7163 ? 1 brief description the CMX7163 qam modem is a half - duplex device supporting multiple channel spacings under host microcontroller ( c) control. its *function image (fi) is loaded to initialise the device and determine modulation types. the7163 fi - 4.x supports 4 - , 16 - and 64 - qam modulations, root raised cosine filtered with ? =0.2, 0.35 or a user programmable filter. the7163 fi - 4.x supports up to 96kbps in a 25khz channel, with channel estimation and equalization to provide robust performance under realistic channel conditions. flexible bit rates support a wide range of applications requiring a selec table bit rate and robustness. the 7163fi - 4.x supports zero if (i/q) transmit and receive. qam data is over - air compatible with the (cmx)7164fi - 4.x. forward error correction and raw modes are available and support user - defined packet structures to suppor t a range of applications. for greater flexibility, different rate fec modes are provided. receive signal quality measurement is supported, making a useful assessment of link conditions. high performance digital if filters may be reconfigured to support m ultiple channel spacings via host command. this feature may eliminate the need to switch between multiple discrete if filters. an integrated analogue interface supports direct connection to zero if i/q radio transceivers with few external components; no external codecs are required. intelligent auxiliary adc, dac and gpio subsystems perform valuable functions and minimise host interaction and host i/o resources. two synthesised system clock generators develop clock signals for off - chip use. the c - bus/sp i master interface expands host c - bus/spi ports to control external devices. *the firmasic ? function image?. the device utilises cmls proprietary firmasic ? component technology. on - chip sub - systems are configured by a function image? data file that is up loaded during device initialisation and defines the device's function and feature set. the function image? can be loaded automatically from a host c over the c - bus serial interface or from an external memory device. the device's functions and features can be enhanced by subsequent function image? releases, facilitating in - the - field upgrades. the CMX7163 , which is available in 64 - pin vqfn and lqfp packages, operates in the range 3.0 to 3.6 volts and embodies selectable powersaving m odes. note that text shown in pale grey indicates features that will be supported in future versions of the device. this data sheet is the first part of a two - part document.
CMX7163 qam modem CMX7163 ? contents section page 1 brief description ................................ ................................ ................................ ...................... 2 1.1 history ................................ ................................ ................................ ........................... 6 2 block diagrams ................................ ................................ ................................ ........................ 9 3 signal list ................................ ................................ ................................ ............................... 11 4 pcb layout guidelines and power supply decoupling ................................ .................... 14 5 external components ................................ ................................ ................................ ............ 15 5.1 xtal interface ................................ ................................ ................................ ............... 15 5.2 c - bus interface ................................ ................................ ................................ .......... 15 5.3 i/q output reconstruction filter ................................ ................................ ................. 16 5.4 i/q input antialias filter ................................ ................................ .............................. 16 5.5 gpio pins ................................ ................................ ................................ ................... 16 6 general descriptio n ................................ ................................ ................................ ............... 17 6.1 CMX7163 features ................................ ................................ ................................ ..... 17 6.2 signal interfaces (i/q tx and rx) ................................ ................................ ............... 18 7 detailed descriptions ................................ ................................ ................................ ............ 19 7.1 xtal frequency ................................ ................................ ................................ ............ 19 7.2 host interface ................................ ................................ ................................ ............. 19 7.2.1 c - bus operation ................................ ................................ ................................ . 19 7.3 function image ? loading ................................ ................................ .......................... 22 7.3.1 fi loading from host controller ................................ ................................ ........... 22 7.3.2 fi loading from serial memory ................................ ................................ ............ 24 7.4 device control ................................ ................................ ................................ ............ 25 7.4.1 normal operatio n overview ................................ ................................ ................. 25 7.4.2 basic tx and rx operation ................................ ................................ .................. 26 7.4.3 device configuration (using the programming register) ................................ .... 27 7.4.4 device configuration (using dedicated registers) ................................ ................ 28 7.4.5 interrupt operation ................................ ................................ ............................... 28 7.4.6 signal control ................................ ................................ ................................ ....... 28 7.4.7 tx mode ................................ ................................ ................................ ............... 29 7.4.8 rx mode ................................ ................................ ................................ ............... 31 7.4.9 carrier sense mode ................................ ................................ ............................. 32 7.4.10 the transmit sequence ................................ ................................ ....................... 34 7.4.11 cmx998 dc offset calibration ................................ ................................ ............ 34 7.4.12 other modem modes ................................ ................................ ........................... 37 7.4.13 data transfer ................................ ................................ ................................ ....... 40 7.4.14 data buffering ................................ ................................ ................................ ...... 41 7.4.15 raw data transfer ................................ ................................ ............................... 42 7.4.16 formatted data transfer ................................ ................................ ...................... 42 7.4.17 pre - loadin g commands ................................ ................................ ....................... 42 7.4.18 gpio pin operation ................................ ................................ ............................. 42 7.4.19 auxiliary adc operation ................................ ................................ ...................... 43 7.4.20 auxiliary dac/ramdac operation ................................ ................................ ...... 44 7.4.21 spi thru - port ................................ ................................ ................................ ....... 45
CMX7163 qam modem CMX7163 ? 7.4.22 spi/c - bus agc ................................ ................................ ................................ .. 46 7.5 digital system clock generators ................................ ................................ ................ 48 7.5.1 main clock operation ................................ ................................ ........................... 48 7.5.2 system clock op eration ................................ ................................ ...................... 49 7.6 signal level optimisation ................................ ................................ ........................... 50 7.6.1 transmit path levels ................................ ................................ ........................... 50 7.6.2 receive path levels ................................ ................................ ............................. 50 7.7 c - bus register summary ................................ ................................ .......................... 51 8 CMX7163 fi - 4.x features ................................ ................................ ................................ ...... 52 8.1 CMX7163 fi - 4.x modulation ................................ ................................ ....................... 52 8.2 CMX7163 fi - 4.x radio interface ................................ ................................ ................ 53 8.2.1 control interface s ................................ ................................ ................................ . 53 8.3 CMX7163 fi - 4.x formatted data ................................ ................................ ............... 54 8.4 receiver response equaliser ................................ ................................ .................... 55 8.5 CMX7163 fi - 4.x typical transmit performance ................................ ........................ 57 8.6 CMX7163 fi - 4.x typical receive performance ................................ ......................... 62 8.6.1 signal t o noise and co - channel ................................ ................................ ........... 62 8.6.2 adjacent channel ................................ ................................ ................................ . 66 8.6.3 receiver dynamic range ................................ ................................ .................... 67 8.6.4 receiver response equaliser performance ................................ ........................ 67 9 performance specification ................................ ................................ ................................ ... 71 9.1 electrical performance ................................ ................................ ............................... 71 9.1.1 absolute maximum ratings ................................ ................................ ................. 71 9.1.2 operating limits ................................ ................................ ................................ ... 71 9. 1.3 operating characteristics ................................ ................................ ..................... 72 9.1.4 CMX7163 fi - 4.x parametric performance ................................ ........................... 77 9.2 c - bus timing ................................ ................................ ................................ ............. 79 9.3 packaging ................................ ................................ ................................ ................... 80 table page table 1 booten pin states ................................ ................................ ................................ ......... 22 table 2 c - bus registers ................................ ................................ ................................ .............. 51 table 3 formatted block types, sizes and rates ................................ ................................ ........ 54 table 4 acr rejection performance ................................ ................................ ............................ 67 figure page figure 1 overall block diagram ................................ ................................ ................................ ...... 9 figure 2 fi - 4.x block diagram C i/q tx and rx ................................ ................................ ............ 10 figure 3 CMX7163 power supply and de - coupling ................................ ................................ ...... 14 figure 4 recommended external components C xtal interface ................................ ................... 15 figure 5 recommended external components C c - bus interface ................................ .............. 15 figure 6 recommended external components C i/q output reconstruction filter ..................... 16 figure 7 CMX7163 i/q tx, i/q rx ................................ ................................ ................................ . 18 figure 8 basic c - bus transactions ................................ ................................ ............................. 20 figure 9 c - bus data streaming operation ................................ ................................ .................. 21 figure 10 fi loading from host ................................ ................................ ................................ .... 23
CMX7163 qam modem CMX7163 ? figure 11 fi loading from serial memory ................................ ................................ ..................... 24 figure 12 host tx data flow (no tx sequence/carrier sense) ................................ ................... 30 figure 13 host rx data flow ................................ ................................ ................................ ........ 31 figure 14 carrier sense ................................ ................................ ................................ ................ 33 figure 15 transmit sequence ................................ ................................ ................................ ....... 34 figure 16 cmx998 dc calibration in terfaces ................................ ................................ ............... 35 figure 17 transmit constellation ................................ ................................ ................................ .. 38 figure 18 constellation diagram C no frequency or phase error ................................ .................. 38 figure 19 constellation diagram C phase error ................................ ................................ ............ 38 figure 20 constellation diagram C frequency error ................................ ................................ ....... 38 figure 21 sample at symbol timing with i/q dc offset diagnostic mode (no frequency error) ....... 39 figure 22 sample at symbol timing with i/q dc offset diagnostic mode (w ith frequency error) .... 39 figure 23 normalised constellation (even with a frequency or phase error) ................................ 40 figure 24 normalised cons tellation (noisy received signal) ................................ ......................... 40 figure 25 command and rx data fifos ................................ ................................ ..................... 41 figure 26 agc using spi thru - port ................................ ................................ .............................. 46 figure 27 agc behaviour during burst reception ................................ ................................ ....... 47 figure 28 main clock generation ................................ ................................ ................................ . 48 figure 29 digital system clock generation schemes ................................ ................................ .. 49 figure 30 qam mappings ................................ ................................ ................................ ............. 52 figure 31 outline radio design (i/q in/out for qam) ................................ ................................ .... 53 figure 32 suggested frame structures ................................ ................................ ........................ 54 figure 33 received 4 and 16 - qam signals, no equalisation ................................ ........................ 56 figure 34 received 4 and 16 - qam signals with equalisation ................................ ....................... 56 figure 35 tx spectrum and modulation measurement configuration for i/q o peration ............... 57 figure 36 tx modulation spectra (4 - qam), 18ksymbols/sec i/q modulation into cmx998 ......... 58 figure 37 tx modulation spec tra (16 - qam), 18ksymbols/sec i/q modulation into cmx998 ....... 59 figure 38 tx modulation spectra (64 - qam), 18ksymbols/sec i/q modulation into cmx998 ....... 60 figure 39 tx modulation spectra (16 - qam), 9k symbols/sec i/q modulation into cmx998 ........ 61 figure 40 modem sensitivity performance ................................ ................................ ................... 62 figure 41 modem co - channel rejection with fm interferer (as en 300 113) ............................. 63 figure 42 4 - qam performance with different coding schemes ................................ .................. 63 figure 43 16 - qam performance with different coding schemes ................................ ................ 64 figure 44 64 - qam performance with different coding schemes ................................ ................ 64 figure 45 comparison of ber and per for 4 - qam modulation ................................ ................... 65 figure 46 comparison of ber and per for 16 - qam modulation ................................ ................. 66 figure 47 comparison of ber and per for 64 - qam modulation ................................ ................. 66 figure 48 4 - qam signal to noise performance, equalised and not equalised ............................ 68 figure 49 16 - qam signal to noise performance, equalised and not equalised .......................... 68 figure 50 64 - qam signal to noise performance, equalised ................................ ........................ 69 figure 51 performance of 16 - qam equalised signals with temperature variation ........................ 70 figure 52 performance of 64 - qam equalised signals with tempera ture variation ....................... 70 figure 53 c - bus timing ................................ ................................ ................................ ............... 79 figure 54 mechanical outline of 64 - pin vqfn (q1) ................................ ................................ ..... 80 figure 55 mechanical outline of 64 - pin lqfp (l9) ................................ ................................ ....... 80 information in this data sheet should not be relied upon for final product design. it is always recommended that you check for the lates t product datasheet version from the cml website: [ www.cmlmicro.com ].
CMX7163 qam modem CMX7163 ? 1.1 history version changes date (d/m/y) 12 ? ? 11 ? ? ? ? ? ? 10 ? ? ? ? ? ? ? ? 9 ? ? ? ? ? ? ? ? ? ? ?
CMX7163 qam modem CMX7163 ? 6 ? remove infor mation indicating that a reset with no fi load is possible. see sections 10.1.1 reset operations, 7.3 function image loading ? fifo level interrupts to the host require re - arming using $50 fifo control. see 10.1.4 fifo control $50 ? include description for "i/ q input dc correction loop gain". see 10.1.10 signal control $61 ? spectrum figure acp mislabeled as for 25khz when it is for 12.5khz ? include over - air symbol sequence for fi - 4 data. see 7.4.15, 10.1.3 and 10.1.26. specifically this matters for bit wise trans fers, indicating which bits are valid ? default values in 10.1.9 to be changed: $07ff becomes $0400; $0801 becomes $0c00 ? addition of "tx done flag set on completion of dc calibration" to 7.4.11, 10.1.18 and 10.1.36. also indicated that auxadc paths, etc in 7 .4.11 are fixed permanently, by changing the description "assumed" to "required" ? figure 27 to show "main pll out" sourced directly from the xtal in idle mode ? update figure 3 12/4/11 5 ? add descriptions for program blocks 8 and 9 ? clarify text at the end of section 11.2.2 ? change b11 to b9 in section 10.1.14 ? remove fi load activation block references and describe default states in section10.1.2 ? clarify bit names in section 10.1.20, to avoid duplication ? add missing action #20 in section 10.2.1 ? add details of th e method of programming the lower part of the rx i/q dc offset ($5f,$60) ? simplify the detail of the system clock architecture ? describe rrc ? =0.2/0.35 option ? added programmable filter option (details on request) ? update i/q output reconstruction filter capa citor values to be preferred values 21/3/11 4 ? clarified the structure of words put into the modem command fifo ? revised recommended crystal tolerance ? revised c - bus clock rate ? revised current drawn by auxdacs ? clarify maximum input signal levels ? improved pr ogramming register settings determining baud rate resulting in improved adjacent channel performance (p1.0 - p1.6). ? improved consistency of naming of signals and registers within the document and when compared to other cml devices. notably auxadc/dac are no w numbered 1 - 4 ? added detail for new fi feature: tx dc calibration when attached to a cmx998 ? added detail for new fi feature: discard symbol count which allows modulation to begin earlier than it would otherwise. ? many editorial changes 6/12/10 3 ? added o utput dc offset lower part control to registers $5d, $5e ? changed default gpio and ramdac setup to manual ? added reg done select register ($69) and changed to description of prg flag to be a type of reg done ? corrections to boot description ? corrected severa l minor typographical and presentational errors. 27/9/2010
CMX7163 qam modem CMX7163 ? 2 ? correction to power supply and de - coupling schematic (figure 3). ? corrected rate documentation error (table in section 8.1). ? improved presentation of v bias and its connections (sections 3, 9.1.3, 10.1.23, etc). ? corrected xtal tolerance specification (now 20ppm recommended). ? updated parametric specifications (sections 9.1.2, 9.1.3 and 9.1.4) following further device characterisation. ? corrected bit description error in section 10.1.5. ? correction of fs found description in section 10.1.25 ? clarify description of preamble/tail configuration and operation (section 10.2.5 program block 3). ? updated the rx and tx examples in sections 11.5 and 11.6 ? corrected several minor typographical and presentational err ors. 1/9/2010 1 ? original document, prepared for first alpha release of fi. 30/4/2010
CMX7163 qam modem CMX7163 ? 2 block diagrams figure 1 overall block diagram gpioa gpiob gpioc gpiod data demodulator channel decoder data modulator transmit functions ioutputp qoutputp auxadc 1 auxadc 2 auxadc 3 auxadc 4 auxdac 1 clk b o o t e n 1 b o o t e n 2 sysclk 1 sysclk 2 auxdac 2 auxdac 3 auxdac 4 a v d d v b i a s a v s s miso mosi auxiliary multiplexed adcs auxiliary dacs system clocks tx data buffer rx data buffer gpio with o / p sequencer fi configured i / o dac 1 dac 2 dac 3 dac 4 ramp - profile ram mux adc 1 thresholds averaging system clock div 1 system clock div 2 registers irqn rdata csn cdata sclk power control spi thru port bias d v d d 3 v 3 d v c o r e d v s s reg . crystal oscillator boot control auxiliary functions receive functions ssout 0 adc 2 thresholds averaging adc 3 thresholds averaging adc 4 thresholds averaging rx data fifo command fifo channel coder main clock pll xtal / clock xtaln system clock pll c - bus interface ssout 1 ssout 2 c - bus / spi thru control agc controller flash boot host thru commands channel filter channel filter ioutputn qoutputn qinputp qinputn iinputp iinputn r e s e t n d a c r e f a d c r e f device reset q i
CMX7163 qam modem CMX7163 ? figure 1 illustrates the overall functionality of the CMX7163 , detailing the auxiliary functions. the following figure expands upon the transmit and receive functions. figure 2 fi - 4.x block diagram C i/q tx and rx i / q demod i adc q adc host c fifo c onstruct f rame : add preamble , framesync and tails channel coder i dac q dac b uffer rf tx i / q mod b uffer rf rx symbol de - mapper ( 4 - , 16 - or 64 - qam ) symbol mapper ( 4 - , 16 - or 64 - qam ) channel dec oder : error correct / detect auto frame sync detect rssi link quality detect cdata rdata fifo csn sclk irqn coded mode data raw mode data r e g i s t e r s raw mode data coded mode data i q pulse - shaping filters channel / pulse - shaping filters q i
CMX7163 qam modem CMX7163 ? 3 signal list 64 - pin q1/l9 signal description pin no. name type 1 gpiob bi general purpose i/o 2 booten1 ip+pu the combined state of booten1 and booten2, upon reset, determine the function image? load interface. reset, determine the function image? load interface. by capacitors mounted close to the device pins. 13 nc nc may also be connected to avss 14 nc nc do not connect 15 nc nc do not connect 16 nc nc may also be connected to avdd 17 ioutputp op differential outputs for i channel; p is positive, n is differential outputs for q channel; p is positive, n is
CMX7163 qam modem CMX7163 ? 64 - pin q1/l9 signal description pin no. name type 27 vbias op internally generated bias v oltage of approximately avdd/2. if vbias is powersaved this pin will be connected via a high impedance to avdd. this pin must be decoupled to avss by a capacitor mounted close to the device pins. 28 iinputp ip differential inputs for i channel signals; p is positive, n is negative. together these are referred to as the i input. 29 iinputn ip 30 adcref adc reference voltage; connect to avss 31 qinputp ip differential inputs for q channel signals; p is positive, n is negative. together these are referred to as the q input. 32 qinputn ip 33 auxadc1 ip auxiliary adc input 1 34 auxadc2 ip auxiliary adc input 2 35 auxadc3 ip auxiliary adc input 3 36 auxadc4 ip auxiliary adc input 4 37 avdd pwr positive 3.3v supply rail for the analogue on - chip circuit. levels and thresholds within the device are proportional to this voltage. this pin should be decoupled to avss by capacitors mounted close to the device pins. 38 avss pwr negative supply rail (ground) for the analogue on - chip circuits. 39 auxda c1 op auxiliary dac output 1 (optionally the ramdac output) 40 auxdac2 op auxiliary dac output 2 41 auxdac3 op auxiliary dac output 3 42 auxdac4 op auxiliary dac output 4 43 dvss pwr negative supply rail (ground) for the digital on - chip circuits 44 dv core pwr digital core supply, nominally 1.8v. by default this will be supplied by an on - chip regulator, although an option is available to use an external regulator. this pin should be decoupled to dvss by capacitors mounted close to the device pins. for d etails see programming register p1.19 in section in 10.2.3 program block 1 C clock contr ol . 45 dvdd3v3 pwr 3.3v positive supply rail for the digital on - chip circuits. this pin should be decoupled to d vss by capacitors mounted close to the supply pins. 46 nc nc do not connect 47 nc nc may also be connected to dvss 48 dvss pwr negative supply rail (ground) for the digital on - chip circuits 49 xtaln op output of the on - chip xtal oscillator inverter 50 xtal/clock ip input to the oscillator inverter from the xtal circuit or external clock source
CMX7163 qam modem CMX7163 ? 64 - pin q1/l9 signal description pin no. name type 51 sysclk1 op synthesised digital clock output 1 52 sysclk2 op synthesised digital clock output 2 53 sclk ip c - bus serial clock input from the c 54 rdata ts op 3 - state c - bus serial data output to the c. this output is high impedance when not sending data to the c. 55 cdata ip c - bus serial data input from the c 56 csn ip c - bus chip select input from the c 57 irqn op wire - orable output for connection t o the interrupt request input of the c. this output is pulled down to dvss when active and is high impedance when inactive. an external pull - up resistor is required. 58 dvcore pwr digital core supply, nominally 1.8v. normally this will be supplied by the on - chip regulator, although an option is available to use an external regulator. this pin should be decoupled to dvss by capacitors mounted close to the device pins. for details see programming register p1.19 in section in 10.2.3 program block 1 C clock contr ol . 59 mosi op spi: master out slave in 60 ssout1 op spi: slave select out 1 61 miso ip spi: master in slave out 62 ssout0 op spi: slave select out 0 63 clk op spi: serial clock 64 gpioa bi general purpose i/o e xposed m etal p ad substrate ~ on this device, the central metal pad (which is exposed on the q1 package only) may be electrically unconnected or, alternatively, may be connected to analogue ground (avss). no other electrical c onnection is permitted. notes: ip = input (+ pu/pd = internal pull - up / pull - down res istor of approximately 75k) op = output bi = bidirectional ts op = 3 - state output pwr = power connection nc = no connection - should not be connected to any signal
CMX7163 qam modem CMX7163 ? 4 pcb layout guidelines and power supply decoupling c20 10f c26 22f c21 10nf c27 10nf c22 10nf c28 10nf c23 10f c31 100nf c24 10nf c25 10nf figure 3 CMX7163 power supply and de - coupling notes: to achieve good noise performance, v dd and v bias decoupling and protection of the receive path from ext raneous in - band signals are very important. it is recommended that the printed circuit board is laid out with a ground plane in the CMX7163 area to provide a low impedance connection between the vss pins and the v dd and v bias decoupl ing capacitors.
CMX7163 qam modem CMX7163 ? 5 external components 5.1 xtal interface x1 for frequency range see 9.1.2 operating limits c1 22pf typical c2 22pf typical figure 4 recommended external components C xtal interface notes: the clock circuit can operate with either a xtal or external clock generator. if using an external clock generator it should be connected to the xtal/clock pin and the xtal and other components are not required. for external clock generator frequency range see 9.1.2 operating limits . when using an external clock generator the xtal oscillator circuit may be dis abled to save power, see 10.2.3 program block 1 C clock contr ol for details. also refer to section 7.1 xtal frequency . the tracks between the xtal and the device pins should be as short as possible to achieve maximum stability and best start up performance. it is also important to achieve a low impedance connection between the xtal cap acitors and the ground plane. the dv ss to the xtal oscillator capacitors c1 and c2 should be of low impedance and preferably be part of the dv ss ground plane to ensure reliable start up. for correct values of capacitors c1 and c2 refer to the documentatio n of the xtal used. 5.2 c - bus interface r2 10k - 100k ? figure 5 recommended external components C c - bus interface note: if the irqn line is connected to other compatible pull - down devices only one pull - up resistor is required on the irqn node.
CMX7163 qam modem CMX7163 ? 5.3 i/q output reconstruction filter the CMX7163 i/q outputs provide internal reconstruction filtering with four selectable bandwidths ( - 3db point shown in section 10.1.22 ). the bandwidth of the internal reconstruction filter may be selected using the i/q output configuration - $b3 write or signal control - $61 write registers. to complete the i/q output reconstruction filter one of the following external rc networks should be used for each of the differential outputs. the external rc network should have a bandwidth that matches the bandwidth of the selected internal reconstruction filter. bandwidth (khz) r3 - r6 (kohms) c9 - c10 (pf) 100 22 33 50 20 75 25 22 150 12.5 22 270 figure 6 recommended external components C i/q output reconstruction filter when transmitting an i/q signal, each i/q output will produce a si gnal with bandwidth half the channel bandwidth. a reconstruction filter with a C 3db point close to half the channel bandwidth will therefore have significant roll off within the channel bandwidth C which is undesirable. an appropriate choice for channels o ccupying up to a 25khz bandwidth (channel bandwidth/2 = 12.5khz) would be a reconstruction filter of 25khz bandwidth. 5.4 i/q input antialias filter the device has a programmable antialias filter in the i/q input path, which is controlled using the i/q input configuration - $b0 write or signal control - $61 write registers. this should be sufficient for most applications, however if additional filtering is required it can be do ne at the input to the device. the input impedance of the i/q input pins varies with the input gain setting, see section 9.1.3 operating characteristics . 5.5 gpio pins all gpio pins are configured as inp uts with an internal bus - hold circuit, after the function image? has been loaded. this avoids the need for users to add external termination (pullup/pulldown) resistors onto these inputs. the bus - hold is equivalent to a 75k resistor either pulling up to logic 1 or pulling down to logic 0. as the input is pulled to the opposite logic state by the user, the bus - hold resistor will change, so that it also pulls to the new logic state. the internal bus - hol d can be disabled or re - enabled using programming register p1.20 in program block 1 C clock contr ol . if the device is reset (either by asserting resetn pin 7, issuing a c - bus general reset or by triggering an inte rnal power on reset) all gpio pins will be immediately configured as inputs. any gpio pins not being pulled either up or down by an external load will be left in a floating state until the function image tm is loaded. to avoid gpio floating input states tha t may somewhat elevate supply current between a reset and function image tm load , it will be necessary to connect pull up or pull down resistors of 220k ? to these pins.
CMX7163 qam modem CMX7163 ? 6 general description 6.1 CMX7163 features the CMX7163 is intended for use in half - duplex modems. transmission takes the form of a data burst consisting of preamble, frame sync and data payload, followed by a tail sequence. reception may utilise the preamble to assist with signal acquisition 1 , but is th en followed by frame sync detection and data decoding. a flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signals. the device includes a xtal clock generator, with phase locked loop a nd buffered output, to provide a system clock output, if required, for other devices. block diagrams of the device are shown in section 2 , block diagrams . tx functions: ? automatic preamble and frame sync insertion simplifies host control ? i/q analogue outputs ? pulse shape filtering ? ramdac capability for pa ramping control ? tx trigger feature allowing precise control of burst start time ? tx burst sequence for automatic ramdac r amp and tx hardware switching ? carrier sense for listen before talk operation ? raw and formatted (channel coded) data modes ? flexible tx coded data block size, up to 416 bytes rx functions: ? automatic frame sync detection simplifies host control ? i/q analogu e inputs ? rx channel filtering and pulse shape filtering ? channel estimation and equalisation ? tracking of symbol timing and input i/q dc offsets ? agc using spi thru - port ? raw and formatted (channel coded) data modes ? flexible rx coded data block size, up to 416 bytes auxiliary functions: ? two programmable system clock outputs ? four auxiliary adcs with six selectable input paths ? spi thru - port for interfacing to synthesisers, cartesian loop ic (cmx998) and other serially controllable devices ? in - build calibration rou tine to support cmx998 cartesian loop transmitter ic ? four auxiliary dacs, one with built - in programmable ramdac interface: ? optimised c - bus (4 - wire, high speed synchronous serial command/data bus) interface to host for control and data transfer, including s treaming c - bus for efficient data transfer ? open drain irq to host ? four gpio pins ? tx trigger input (provided by gpioa) ? serial memory or c - bus (host) boot mode 1 the frame sy nc detection algorithm of the CMX7163 is capable of detecting a frame sync without having bit synchronisation, so preamble is not required for obtaining bit sync. some preamble is still needed to ensure that the b eginning of the frame sync is transmitted and received without distortion. preamble may also be used to provide a known signal on which to acquire i/q dc offset corrections.
CMX7163 qam modem CMX7163 ? both transmit and receive data can be raw or coded data blocks . fi - 4.x provide s a variety of coding rates for flexibility and very large block sizes having the potential to improve performance in fading conditions considerably. 6.2 signal interfaces (i/q tx and rx) fi - 4.x produces qam modulation. the transmitted signal is provided as an i/q baseband, for mixing up onto an rf carrier, with amplification. for reception an i/q baseband signal should be interfaced into the CMX7163 fi - 4.x . as the i/q interface pr ovides amplitude information, the rssi signal is calculated internally. it is averaged in order to produce the rssi measurement and to support the carrier sense decision whether to transmit. figure 7 CMX7163 i/q tx, i/q rx radio receiver cmx 7163 transmit processing t / r ioutput qoutput iinput qinput receive processing mix onto rf carrier and linearise if required
CMX7163 qam modem CMX7163 ? 7 detailed descriptions 7.1 xtal frequency the CMX7163 is designed to work with a xtal, or an external frequency oscillator within the ranges specified in section 9.1.3 operating characteristics . program block 1 (see user manual) must be loaded with the correct values to ensure that the device will work to specification with the user selected clock frequency. a table of configuration values can be found in table 8 supporting baud rates up to 20k symbols per second when the xtal frequency is 9.6mhz or the external oscillator frequency is 9.6 or 19.2 mhz. rates other than those tabulated (within this range) are possible, see section 10.2.3 program block 1 C clock contr ol . further information can be provided on request. the modem can oper ate with a clock or xtal input frequency tolerance of 50ppm. the receive performance will be compromised as the system tracks, so a maximum tolerance of 20ppm is recommended. 7.2 host interface a serial data interface (c - bus) is used for command, status and da ta transfers between the CMX7163 and the host c; this interface is compatible with microwire?, spi? and other similar interfaces. interrupt signals notify the host c when a change in status has occurred; the c should read the irq status register across the c - bus and respond accordingly. interrupts only occur if the appropriate mask bit has been set, see interrupt operation . 7.2.1 c - bus operation this block provides for the tra nsfer of data and control or status information between the CMX7163 internal registers and the host c over the c - bus serial bus. single register transactions consist of a single register address byte sent from the c, which may be f ollowed by a data word sent from the c to be written into one of the CMX7163 s write - only registers, or a data word read out from one of the CMX7163 s read - only registers. streaming c - bus transactions consist of a single register address byte followed by many data bytes being written to or read from the CMX7163 . all c - bus data words are a multiple of 8 bits wide, the width depending on the source or destination register. note that certain c - bus transactions require only an address byte to be sent from the c, no data transfer being required. the operation of the c - bus is illustrated in figure 8 . data sent from the c on the cdata (command data) li ne is clocked into the CMX7163 on the rising edge of the sclk input. data sent from the CMX7163 to the c on the rdata (reply data) line is valid when sclk is high. the csn line must be held low during a data t ransfer and kept high between transfers. the c - bus interface is compatible with most common c serial interfaces and may also be easily implemented with general purpose c i/o pins controlled by a simple software routine. section 9.2 c - bus timing gives detailed c - bus timing requirements. note that, due to internal timing constraints, there may be a delay of up to 60s between the end of a c - bus write operation and the de vice reading the data from its internal register.
CMX7163 qam modem CMX7163 ? c - bus single byte command (no data) note: the sclk line may be high or low at the start and end of each transaction. ? c - bus n - bit register write csn sclk cda ta 7 6 5 4 3 2 1 0 n - 1 n - 2 n - 3 2 1 0 msb address lsb msb write data lsb rdata hi - z c - bus n - bit register read csn sclk cdata 7 6 5 4 3 2 1 0 msb address lsb rdata hi - z n - 1 n - 2 n - 3 2 1 0 msb read data lsb data value unimp ortant repeated cycles either logic level valid (and may change) either logic level valid (but must not change from low to high) figure 8 basic c - bus transactions csn sclk cdata 7 6 5 4 3 2 1 0 msb address lsb rdata hi - z
CMX7163 qam modem CMX7163 ? to increase the data bandwidth between the c and the CMX7163 , certain of the c - bus read and write registers are capable of data - streaming operation. this allows a single address byte to be followed by the transfer of multiple read or write data words, all within the same c - bus tra nsaction. this can significantly increase the transfer rate of large data blocks, as shown in figure 9 . example of c - bus data - streaming (8 - bit write register) csn sclk cdata 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 add ress first byte second byte last byte rdata hi - z example of c - bus data - streaming (8 - bit read register) csn sclk cdata 7 6 5 4 3 2 1 0 address rdata hi - z 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 first byte second byte last byte data value unimportant repeated cycles either logic level valid (and may change) either logic level valid (but must not change from low to high) figure 9 c - bus data streaming operation notes: 1. for comma nd byte transfers only the first 8 bits are transferred ($01 = reset) 2. for single byte data transfers only the first 8 bits of the data are transferred 3. the cdata and rdata lines are never active at the same time . the address byte determines the data directi on for each c - bus transfer. 4. the sclk can be high or low at the start and end of each c - bus transaction 5. the gaps shown between each byte on the cdata and rdata lines in the above diagram are optional, the host may insert gaps or concatenate the data as requ ired.
CMX7163 qam modem CMX7163 ? 7.3 function image ? loading the function image ? (fi), which defines the operational capabilities of the device, may be obtained from the cml technical portal, following registration. this is in the form of a 'c' header file which can be included into th e host controller software or programmed into an external serial memory. the function image tm size can never exceed 128 kbytes, although a typical fi will be considerably less than this. note that the booten1/2 pins are only read at power - on, when the rese tn pin goes high, or following a c - bus general reset, and must remain stable throughout the fi loading process. once the fi load has completed, the booten1/2 pins are ignored by the CMX7163 until the next power - up or reset. the booten1/2 pins are both fitted with internal low current pull - up devices. for serial memory load operation, booten2 should be pulled low by connecting it to dv ss either directly or via a 47k resistor (see table 1 ). whilst booting the boot loader will return the checksum of each block loaded in the c - bus rx data fifo. the checksums can be verified against the published values to ensure that the fi has loaded correctly . once the fi has been loaded, the CMX7163 performs these actions: (1) the product identification code ($7163) is reported in the c - bus rx data fifo (2) the fi version code is reported in c - bus rx data fifo. table 1 bo oten pin states booten2 booten1 c - bus host load 1 1 reserved 1 0 serial memory load 0 1 reserved 0 0 7.3.1 fi loading from host controller the fi can be included into the host controller software build and downloaded into the CMX7163 at power - up over the c - bus interface, using the command fifo. for function image ? load, the fifo accepts raw 16 - bit function image ? data (using the modem command fifo word) - $49 write register, there is no need for distinction betwe en control and data fields. the booten1/2 pins must be set to the c - bus load configuration, the CMX7163 powered or reset, and then data can then be sent directly over the c - bus to the CMX7163 . if the host detects a brownout, the booten1/2 pins should be set to re - load the fi. a general reset should then be issued or the resetn pin used to reset the CMX7163 and the appropriate fi load procedure followed. streaming c - bus may be used to load the modem command fifo word - $49 write register with the function image ?, and the modem command fifo level - $4b read register used to ensure that the fifo is not allowed to overflow during the load process. the download time is limited by the clock frequency of the c - bus; with a 5mhz sclk it should take less than 250ms to complete even when loading the largest possible function image ? .
CMX7163 qam modem CMX7163 ? figure 10 fi loading from host booten 2 = 1 booten 1 = 1 power - up or write general reset to cmx 7163 write start block n address ( db n _ ptr ) to cmdfifo word - $ 49 write up to 128 - fifo fill level words to cmdfifo word - $ 49 end of block ? read and verify 32 - bit checksum words from rxfifo word - $ 4 d is the next block the activation block ? write start block n address ( activate _ ptr ) to cmdfifo word - $ 49 write start block n length ( activate _ len ) to cmdfifo word - $ 49 poll status - $ 7 e until reg done b 14 = 1 ( prg flag is unmasked in reg done select register - $ 69 by default and indicates when the fi is loaded ) booten 1 and booten 2 may be changed once it is clear that the cmx 7163 has comitted to c - bus boot C i . e . when a word has been read from the c - bus command fifo read the product id code and the fi version code from the rxfifo word - $ 4 d write block 1 length ( db n _ len ) to cmdfifo word - $ 49 check cmdfifo level - $ 4 b no yes no C load next block block number n = 1 n = n + 1 yes cmx 7163 is now ready for use read the rxfifo level - $ 4 f until 3 device check words appear in rxfifo word - $ 4 d . read and discard them booten 1 booten 2 v dd
CMX7163 qam modem CMX7163 ? 7.3.2 fi loading from serial memory the fi must be converted into a format for the serial memory programmer (normally intel hex) and loaded into the serial mem ory either by the host or an external programmer. the serial memory should contain the same data stream as written to the command fifo shown in figure 10 . the most significant byte of each 16 - bit word should be sto red first in serial memory. the serial memory should be interfaced to the CMX7163 spi thru - port using ssout0 as the chip select. the CMX7163 needs to have the booten pin s set to serial memory load, and then on power - on, following the resetn pin becoming high, or following a c - bus general reset, the CMX7163 will automatically load the data from the serial memory without interventi on from the host controller. figure 11 fi loading from serial memory the CMX7163 has been designed to function with the at25f 512 serial flash device, however other manufacturers' parts may also be suitable. the time taken to load the fi should be less than 500ms even when loading the largest possible function image ? . booten 2 = 0 booten 1 = 1 power - up or write general reset to cmx 7163 poll status - $ 7 e until reg done b 14 = 1 ( prg flag is unmasked in reg done select register - $ 69 by default and indicates when the fi is loaded ) booten 1 and booten 2 may be changed from this point on , if required cmx 7163 is now ready for use read and verify the 32 - bit checksum word of each block loaded C found in the rxfifo word - $ 4 d read the product id code and the fi version code from the rxfifo word - $ 4 d read and discard 3 device check words from the rxfifo word - $ 4 d . booten 1 booten 2 vdd jumper for programming serial memory ( if required )
CMX7163 qam modem CMX7163 ? 7.4 device control once the function image ? is loaded the CMX7163 can be set into one of four main modes using the modem mode and control - $6b write register: ? idle mode C for configuration or low power operation ? transmit mode C for tra nsmission of raw or formatted data ? receive mode C for detection and reception of bursts containing raw or formatted data ? carrier sense mode C for attempting to transmit if the channel is free, otherwise continuing to receive these four modes are described in the following sections . all control is carried out over the c - bus interface: either directly to operational registers in transmit, receive and carrier sense modes or, for parameters that are not likely to change during operation, using the programming register - $6a write in idle mode. to conserve power when the device is not actively processing a signal, place the device into idle mode. additional power - saving can be achieved by disabling unused hardware blocks, however, most of the hardware power - saving is automatic. note that v bias must be enabled to allow any of the input or output blocks to function . it is only possible to write to the programming register whilst in idle mode . see: ? 10.1.17 programming register - $6a write ? 10.1.18 modem mode and control - $6b write ? 10.2 programming register operation ? 10.1.24 vbias con trol - $b7 write . 7.4.1 normal operation overview in normal operation (after the CMX7163 is configured) the appropriate mode must be selected and data provided in transmit or retrieved in receive . this process is carried out by selecting the mode (tx, rx or carrier sense), selecting the frame sync to use (frame sync 1 or 2) and selecting formatted or raw data . such a selection is required at the beginning of transmission or reception of a burst. in transmit (or following a carrier sense period where no signal is detected on channel) the CMX7163 will begin by switching gpio signals as configured by the transmit sequence . the ramdac can also be configured to ramp up at this point . transmission then begins with preamble and the selecte d frame sync . the main payload of user data comes next, ending with selectable tail bits. the burst ends with the transmission sequence ramping the ramdac down and/or switching gpio signals. in receive (or following a carrier sense period where signal is d etected on channel) the CMX7163 will begin by searching for either or both of the configured frame sync patterns . on detection of a frame sync, reception and delivery of rx data will begin . reception continues unt il the CMX7163 is switched into a different mode, determined by the host. during the burst, data must be transferred into or out of the CMX7163 . transfers use the command fifo to transfer data and commands about data type into the CMX7163 , and the rx fifo to transfer data out of the CMX7163 . the irq status register is used to indicate tha t the data has been dealt with . the CMX7163 can be configured to interrupt the host when a specified data block has been transferred, or on fifo fill level. the CMX7163 o ffers internal buffering of data in addition to the command and rx fifos in both receive and transmit directions . the amount of buffering offered is dependant on the mode in which the device is operating . in the process of burst transmission or reception t he most significant registers are: ? 10.1.18 modem mode and control - $6b write ? 10.1.37 irq status - $7e read ? 10.1.19 irq mask - $6c write ? 10.1.3 modem command fifo data/control - $48, $49 and $4a write ? 10.1.26 receive fifo data/control - $4c, $4d, $4e read ? 10.1.25 modem command fifo level - $4b read ? 10.1.27 receive fifo level - $4f read .
CMX7163 qam modem CMX7163 ? 7.4.2 basic tx and rx operation the CMX7163 has many features that provide a great deal of flexibility, but basic data transmission and reception can be carried out fairly easily by understanding the operation of just a few registers. there are other ways of controlling signal transmission an d reception but a basic example is given below: basic transmit operation transmission of raw data bytes uses the following procedure: c - bus operation action description write $0080 to fifo control - $50 write fl ush the command fifo to ensure that no data is remaining from previous transmissions write $18 to the modem command fifo control byte (see modem command fifo data/control - $48, $49 and $4a write ) select 8 byte da ta blocks selects blocks of data bytes to be transmitted C 8 bytes in each, after which the CMX7163 will request more data from the host write 8 data bytes to the modem command fifo data byte - see modem command fifo data/control - $48, $49 and $4a write pre load the command fifo with data to transmit this provides a buffer of 8 data bytes before transmission starts, so that the host does not need to write data as promptly for the rest of t he burst write $0042 to modem mode and control - $6b write start transmission initiates a transmission with preamble, frame sync 1 and then the pre loaded data poll the irq status - $7e read register for bit 8 C cmd done = 1 wait until the data block has been read from the fifo when this is complete a further 8 data bytes may be written to the modem command fifo data byte (see modem command fifo data/control - $48, $49 and $4a write ) and the irq status - $7e read register polled again. this step may be repeated as many times as needed write $f000 to the modem command fifo word (see modem command fifo data/control - $48, $49 and $4a write ) indicate burst end is intended indicate that no more data is to follow C so when the data loaded into the command fifo is modulated the CMX7163 will terminate the burst with tail bits poll the irq status - $7e read register for bit 9 C tx last tail = 1 wait until the burst ends the burst has completed, with all data and tail bits having been modula ted. it is now possible to transition to other modes, or transmit another burst using the modem mode and control - $6b write register the procedure described above can be adapted, making transmission of differen t numbers of bytes, bits or coded blocks possible. basic receive operation reception of raw data bytes uses the following procedure: c - bus operation action description write $8000 to fifo control - $50 write flu sh the command fifo to ensure that no data is remaining from previous data reception write $1400 to the modem command fifo word (see modem command fifo data/control - $48, $49 and $4a write ) select 4 byte data blo ck reception C C this will continue until the mode is changed
CMX7163 qam modem CMX7163 ? c - bus operation action description write $0033 to rx tracking - $66 w rite select tracking modes selects automatic i/q dc offset correction and symbol timing tracking write $0401 to modem mode and control - $6b write start reception initiates a frame sync search, searching for frame sync 1. once it is detected then rx data will be made available - apply input signal the input signal should contain preamble, frame sync 1 and then raw data. the frame sync should be detected and rx data made available poll the irq status - $7e read register for bit 8 C cmd done = 1 wait for data this indicates that the 4 data bytes requested have been received and are available read the receive fifo data byte (see receive fifo data/control - $4c, $4d, $4e read ) 4 times retrieve the received data data is read from the receive data fifo. once 4 data bytes are read the irq status register may be polled again to check if more data is availab le if required, and then those data bytes read. this step may be repeated as many times as needed - end of reception once enough data has been received a mode change (using the modem mode and control - $6b write r egister) will stop reception or start searching for another frame sync the procedure described above can be adapted, making reception of different numbers of bytes, bits or coded blocks possible. the registers used for basic transmission and reception ar e: ? 10.1.18 modem mode and control - $6b write ? 10.1.37 irq status - $7e read ? 10.1.3 modem command fifo data/control - $48, $49 and $4a write ? 10.1.26 receive fifo data/control - $4c, $4d, $4e read ? 10.1.4 fifo control - $50 write ? 10.1.1 5 rx tracking - $66 w rite 7.4.3 device configuration (using the programming register) while in idle mode the programming register becomes active. the programming register provides access to the program blocks. program blocks allow configuration of the CMX7163 during major mode change. features that can be configured include: ? flexible selection of baud rates, from 2k to 20k baud ? pre - amble and frame syncs to be using in transmit and receive ? selection of automatic control of 4 x gpio and the ramdac during transmission ? configuration of ramdac profile ? configuration of rssi averaging ? configuration of the carrier sense window and thresholds ? configuration of system clock outputs ? configuration of spi thru - port rate and word format ? configurat ion of agc commands using the spi thru - port. full details of how to configure these aspects of device operation are given in section 10.2 in the user manual.
CMX7163 qam modem CMX7163 ? 7.4.4 device configuration (using dedicated registers) som e device features may be configured using dedicated registers . this allows for configuration outside of idle mode . configuration of the following features is possible: ? auxiliary adc detect thresholds ? auxiliary adc input selection and averaging mode ? output gain ? output dc offsets ? selection of agc mode, or manual control of the gain level. the registers that allow configuration of these features are: ? 10.1.8 i/q output contro l - $5d, $5e write ? 10.1.9 i/q input control - $5f, $60 write ? 10.1.21 i/q input coarse gain - $b1, $b2 write ? 10.1.23 i/q output coarse gain - $b4, $b5 write ? 10.1.22 i/q output configuration - $b3 write ? 10.1.20 i/q input configuration - $b0 write ? 10.1.5 auxadc1 - 4 control - $51 to $54 write ? 10.1.6 auxadc1 - 4 threshold - $55 to $58 write ? 10.1.10 signal control - $61 write ? 10.1.14 agc control - $65 write . 7.4.5 interrupt operation the CMX7163 can produce an i nterrupt output when various events occur . examples of such events include detection of a frame sync, an overflow of the internal data buffering in receive, or completion of transmission whilst in transmit. each event has an associated irq status register bit and an irq mask register bit. the irq mask register is used to select which status events will trigger an interrupt on the irqn line. all events can be masked using the irq mask bit (bit 15) or individually masked using the irq mask register. enabling an interrupt by setting a mask bit (0 ? 1) after the corresponding irq status register bit has already been set to 1 will also cause an interrupt on the irqn line. the irq bit (bit 15) of the irq status register reflects the irqn line state. all interrupt fl ag bits in the irq status register are cleared and the interrupt request is cleared following the command/address phase of a c - bus read of the irq status register. see: ? 10.1.37 irq status - $7e read ? 10.1.19 irq mask - $6c write . 7.4.6 signal control the CMX7163 offers two signal inputs (i input, q i nput), and two modulator outputs (i output, q output). the analogue gain/attenuation of each input and output can be set individually. during i/q modulation transmit, i output and q output will output in - phase and quadrature output signals. they may be ind ependently inverted and their gains changed. during i/q modulation receive, i input and q input will accept in - phase and quadrature modulated signals. they may be independently inverted and their gains changed. note: when transmitting (or receiving) in i/ q mode it may be necessary to swap the i and q signals. this effect can be achieved by negating either the i or q signals.
CMX7163 qam modem CMX7163 ? see: ? 10.1.8 i/q output contro l - $5d, $5e write ? 10.1.9 i/q input control - $5f, $60 write ? 10.1.21 i/q input coarse gain - $b1, $b2 write ? 10.1.23 i/q output coarse gain - $b4, $b5 write ? 10.1.22 i/q output configuration - $b3 write ? 10.1.20 i/q input configuration - $b0 write . 7.4.7 tx mode in typical tx operation, the preamble and fs1 or fs2 are transmitted automatically, and then data from the command fifo is transmitted directly until a txend command is processed or the mode is changed to rx or idle. data may be written to the command fifo prior to starting transmission, enabling the host to create a buffer of data and therefore a voiding risk of the data running out during transmission. further buffering is provided to expand the amount of data that may be absorbed by the CMX7163 . the host should write the initial data to the command fifo and then set modem control to the required transmit type with the mode bits as tx. as soon as the data has been read from the c - bus txdata registers the cmd done irq and/or command fifo irq will be asserted (when configured correctly). more data should be loaded into the command fifo at this stage before data buffered in the CMX7163 runs out, otherwise an under - run will occur. to end the burst the host should send a txend command, signalling to the CMX7163 that the burst is to end, and the imminent data under - run is intentional. it is possible to define a transmission sequence with defined ramdac ramp up/down, and gpio on/off events. the transmission sequence is configured using program block 5. for precise control of the instant that transmission starts it is possible to trigger a transmission using gpioa as an input. selecting a tx mode with gpioa configured as an automatic input places the device into a tx pending sta te, where it is neither receiving nor transmitting, just waiting for a trigger on gpioa to begin transmission. in general figure 12 describes operation when a transmit sequence is defined by the host by: ? removing the need for the host to provide a ramp up C instead the configured tx sequence will deal with this ? inserting gpio on/off events before ramp up and after ramp down as specified by the transmit sequence.
CMX7163 qam modem CMX7163 ? figure 12 host tx data flow (no tx sequence/carrier sense) load data to c ommand fifo set modem control totx preamble , frame sync and required data mode , mode = tx irq = command fifo lvl / datardy ? no the modem will transmit the preamble , frame sync and data the host should ensure that any external hardware is also set into tx mode ( if not automatically controlled by the gpio pins ). note : yes more data to send ? load data to command fifo yes no see rx _ process flow diagram note : set modem control to idle : mode = idle the host should ensure that any external hardware is also set into idle mode ( if not automatically controlled by the gpio pins ). note : goto rx _ process goto idle mode this assumes that : the transmit control sequence and frame syncs have been configured using the programming register note : tx _ process irq = txdone ? no yes irq = error , modem status = underflow may occur at this point , if enabled . note : due to internal processing delays in the filters etc , the h ost should wait for irq = txdone or implement its own delay to ensure all data has been transmitted . note : execute ramdac ramp down execute ramdac ramp up no ensure that ramdac speed is fast enough to allow for hardware and internal processing delays note : tx triggered on gpio ? gpio tx trigger here the device is waiting for a gpio trigger to start the transmission attempt . as no carrier sense is selected it is not receiving and is committed to transmit note : wait for tx trigger yes yes load txend command
CMX7163 qam modem CMX7163 ? 7.4.8 rx mode in rx mode a frame sync must be detected, then data is supplied to the host through the rx data fifo and should be read in response to a cmd done irq/rx data fifo irqs (when configured). the CMX7163 will continue decoding the input waveform until the host sets the mode bits to either tx or idle, as required. once initial timing is established, timing corrections can be derived from the data to tra ck the received signal. the rx tracking register allows selection of the tracking mode used to track the signal level, i/q dc offset and symbol timing of the input signal as required. use of the automatic tracking modes is recommended. figure 13 host rx data flow rx _ process load command fifo with rx data command ( s ). set modem control to rx and receive either framesync . irq = datardy or rx fifolvl ? no t he modem will start to look for frame sync . the host should ensure that any external hardware is also set into rx mode ( if not automatically controlled by the gpio pins ). note : yes more data to receive ? load data from rx fifo yes no see tx _ process flow diagram note : set modem control to idle t he modem will drop into idle mode . the host should ensure that any external hardware is also set into idle mode ( if not automatically controlled by the gpio pins ). note : no goto tx _ process goto idle _ process d ata may be in variable size blocks and / or may be processed irregularly by the host note : if enabled , irq = framesync will occur before irq = datardy note : an irq = datardy may still be pending at this point note : load command fifo with further rx data command ( s ) further data is requested the device will buffer data internally . therefore an internal data overflow can occur if the command fifo is not written promptly . note : transmission required ? yes
CMX7163 qam modem CMX7163 ? 7.4.9 carrier sense mode carrier sense mode is a receive mode, pending a transmission. a carrier sense period, averaging window length and threshold must be defined in the program blocks prior to entering this mode. when the CMX7163 is in i/q receive mode the signal strength is calculated internally C as the i/q signal contains amplitude information. on entry to carrier sense mode, reception will begin (o r continue if the previous mode was receive) with an attempt to search for a frame sync. during the defined carrier sense period average rssi will be computed over a moving window. three outcomes are possible: 1. if during the carrier sense period the averag e rssi is above the carrier sense threshold then transmission will be aborted, and search for frame sync will continue. the device reverts to receive. 2. there is a possibility that a valid frame sync will be detected during the carrier sense period. if this is the case, the transmission will be aborted immediately and the device reverts to receive. 3. if the rssi average remains below the carrier sense threshold then transmission will proceed. in each of the three possible cases, status bits will be used to ind icate the result of the carrier sense period. if the carrier sense mechanism is used in conjunction with gpioa as a tx trigger, operation is as follows: the device is put in receive, searching for a frame sync. if frame sync is found during this period th en it is indicated to the host via the status bits and normal reception resumes. no carrier sense happens until gpioa is used to start the transmit process, at which point carrier sense begins and operation is as described above. note: the command fifo an d command buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7163 reverting to receive mode. this is to avoid accidentally processing transmit commands pre - loaded by th e host as receive commands. this is the only situation in which the fifos or buffers will be flushed other than by direct host instruction.
CMX7163 qam modem CMX7163 ? figure 14 carrier sense clear c ommand fifo set modem control totx preamble , frame sync and required data type , rx frame sync and required data type . mode = carrier sense irq = fs received no irq = cs abort no yes this assumes that : a carrier sense threshold and period have been defined using the programming register note : carrier sense process irq = cs tx yes here the device is in receive and searching for a frame sync , as well as monitoring rssi ( carrier sensing ) note : rx process yes tx process tx triggered on gpio ? no yes irq = fs received rx process gpio tx trigger carrier sense begins here the device is in receive and searching for a frame sync , as well as waiting for a gpio trigger to start the transmission attempt note : wait for tx trigger yes yes
CMX7163 qam modem CMX7163 ? 7.4.10 the transmit sequence the CMX7163 is capable of being configured to provide the following features: 1. selecting tx mode results in transmission starting directly on entry to tx mode or is delayed until gpioa is used as an input trigger 2. selecting ca rrier sense mode will result in behaviour as in point 1, followed by a carrier sense period, where transmission is delayed (reception continues) until a carrier sense period is completed and no activity is sensed on the channel 3. selecting tx calibration wil l cause cmx998 cartesian loop dc calibration to be carried out prior to transmission, as part of the programmable transmit sequence. see section 7.4.11 cmx998 dc offset calibration for details. 4. once started, transmission can be configured to be a simple modulation output or can include a programmable sequence of events including ramdac ramp up/down and gpio on/off. each of these operations can be selected independently of the others. the following diagram illustrates transmit operation. figure 15 transmit sequence 7.4.11 cmx998 dc offset calibration the CMX7163 may be interfaced to a cmx998 cartesian loop ic . the cmx998 is used to provide linearisation of the power amplifier used to transmit the modulation produced by the CMX7163 . if the signal produced by the CMX7163 when no modulation is present does not exactly match the dc referenc e of the cmx998, carrier leakage will result. this worsens the transmitted signal quality. dc offset calibration is intended to significantly reduce the carrier leakage. tail bits preamble / sync modem control mode reception active ( high ) ramdac output carrier sense tx trigger input ( gpioa ) tx on outputs ( gpioa - d ) time pre - tx , in receive awaiting tx trigger on gpioa , if configured carrier sense - if selected may cause abort to rx at any point . transmit sequence C ramdac and gpio on / off if configured tx ended modulation out active if mode = cs , inactive if mode = tx data payload mode = rx mode = cs or tx transmit calibration cal cmx 998 dc offset cal .
CMX7163 qam modem CMX7163 ? the cmx998 cartesian feed - back loop transmitter datasheet and an application note cm x998 cartesian feedback loop dc calibration are both available from the cml website ( www.cmlmicro.com ) and should be referred to for a more in - depth understanding of the need for dc offset calibration. the CMX7163 performs automatic dc offset calibration as either part of a transmit sequence or in a separate calibration stage. dc offset calibration determines the dc offset that should be applied to the i output and q output signals by the CMX7163 to minimise carrier leakage. the results of calibration will be held by the CMX7163 for use in later transmissions and are made available to the host. the interface is required to be as shown in figure 16 cmx998 dc calibration interfaces . figure 16 cmx998 dc calibration interfaces during calibration the cmx998 is controlled by the CMX7163 using the spi thru - port (the cmx998 is as sumed to be device 1) to select one of the following to be output to the cmx998 dcmeas output: i reference the cmx998 dc reference for the in - phase signal path q reference the cmx998 dc reference for the quadrature signal path i error (low/high ga in 2 ) the cmx998 measure of the dc produced by the input signal on the in - phase signal path q error (low/high gain) the cmx998 measure of the dc produced by the input signal on the quadrature signal path during calibration the CMX7163 uses a uxadc2 to measure reference i and reference q. it then outputs a dc level on the i output, q output signals. auxadc2 is used to measure the dcmeas i and q error and i output, q output are adjusted to make the dcmeas i and q errors equal to the dcmeas i ref erence and q reference measurements. 2 the low and high gain states are created by adjusting the gain of the error ampl ifiers in the cmx998, see the cmx998 datasheet for more information. cmx 7163 cmx 998 a a i output q output b dcmeas auxadc 2 c spi thru - port ( chip sel = ssout 1 ) c - bus in q input i input b . auxadc 2 is used to sample dcmeas C to measure reference signals and error signals c . the spi thru - port is used to control the cmx 998 C selecting reference i / q and error i / q as measurements , as well as high gain / low gain modes of the cmx 998 a . the cmx 7163 i and q outputs are used to provide dc levels , which are adjusted to make the error i / q measurements equal to the reference i / q measurements d auxdac 1 ( ramdac ) pa cntrl d . the ramdac is typically used to ramp the pa control voltage up after calibration is complete . this is not a part of the calibration sequence , but may be active as part of the transmit sequence .
CMX7163 qam modem CMX7163 ? there are three complications to this process: 1. the total gain of the feedback loop i output to cmx998 dcmeas error signal to auxadc is unknown C so the adjustment to the i output signal may not be calculated completel y accurately from a single measurement. therefore the gain applied to the calculated adjustment may be programmed and a number of iterations selected, resulting in a damped feedback loop. 2. the dc error to be corrected is usually large enough that if measure d with the cmx998 in high gain mode the dcmeas output would saturate. this makes calculation of the magnitude of error impossible. therefore low gain mode should be used initially. 3. when changing from low to high gain modes the circuit changes (see dc calib ration application note referenced earlier), therefore the correction needed changes. however the low gain correction should at least be close to bringing the high gain measurement out of saturation. the relationship between correction computed using low g ain and high gain is consistent C so may be noted and applied as an offset. the calibration sequence implemented in the CMX7163 has the following stages: setup initialise the ssp port, auxadc and select refi as dcmeas output from the cmx998 refi read refi, select dcmeas = refq refq read refq, select dcmeas = errori errorilo read errori assuming low gain and adjust the i output accordingly errorqlo read errorq assuming low gain and adjust the q output accordingly iterate C go to errori lo after a delay for corrected signals to settle highgain select high gain mode of the cmx998, apply low to high gain mode correction errorqhi read errorq assuming high gain and adjust the q output accordingly errorihi read errori assuming high gain and adjust the i output accordingly iterate C go to errorqhi after a delay for corrected signals to settle tidyup restore the cmx998, to its stage pre - calibration C ready to output modulation note: despite no modulation being produced, the tx done flag o f irq status - $7e read register will be set at the completion of the cmx998 dc offset calibration task. the timings of each calibration step can be configured using p4. 8 : set legacy timing mode b0 adc sample delay 0 - minimal delay mode (gives a delay of 1.2 symbol times) 1 - legacy delay mode (gives a delay of 8.2 symbol times) b1 tx done and tx last tail indication timing 0 - selects minimal jitter of +/ - 0.6 symbol times for tx done and tx last tail indication timing. enables the use of the p4.9 delay adjustment control for tx done and tx last tail indication timing. adjusting these delays enables indication timing to be changed to better match any changes in tx pulse shaping filter delay or for other user purposes. 1 - legacy timing delay mode (delay not specified; delay and jitter behaviours will be consistent so long as the number of data field symbols, number of tai l symbols, and other factors are not changed) b2 - 15 reserved reserved C p4. 9 : set tx done delay
CMX7163 qam modem CMX7163 ? only if p4.8 b1=0 then this controls the delay in indicating tx done and tx last tail indications, in units of 1.2 symbol times. the default value makes tx done indication coincide with when the end of the last data field symbol analog signal is produced at the cmx7164 ioutput and qoutput pins when the default tx pulse shaping filter is engaged. the user may adjust this parameter value to suit the di fferent delay of any other different pulse shaping filter used. p4. 10 : offset tx end sequence start time adjusts the tx end sequence start time to be earlier than the default time. adjustment is in symbols. program block 5 C burst tx sequence . to reduce calibration time a calibration sequence may be configured that o mits some stages of the calibration process. however there must always be a setup and tidyup stage, and if errorqhi and errorihi are included then the high gain stage must be included as well. the registers used during tx dc offset calibration are: ? 10.1.18 modem mode and control - $6b write ? 0 ? p4. 8 : set legacy timing mode ? b0 adc sample delay 0 - minimal delay mode (gives a delay of 1.2 symbol times) 1 - legacy delay mode (gives a delay of 8.2 symbol times) b1 tx done and tx last tail indication timing 0 - selects minimal jitter of +/ - 0.6 symbol times for tx done and tx last tail indication timing. enables the use of the p4.9 delay adjustment control for tx done and tx last tail indication timing. adjusting these delays enables indication timing to be changed to better match any changes in tx pulse shaping filter delay or for other user purposes. 1 - legacy timing delay mode (delay not specified; delay and jitter behaviours will be consistent so long as the number of data field symbols, number of tai l symbols, and other factors are not changed) b2 - 15 reserved reserved C p4. 9 : set tx done delay only if p4.8 b1=0 then this controls the delay in indicating tx done and tx last tail indications, in units of 1.2 symbol times. the default value makes tx done indication coincide with when the end of the last data field symbol analog signal is produced at the cmx7164 ioutput and qoutput pins when the default tx pulse shaping filter is engaged. the user may adjust this parameter value to suit the di fferent delay of any other different pulse shaping filter used. p4. 10 : offset tx end sequence start time adjusts the tx end sequence start time to be earlier than the default time. adjustment is in symbols. ? program block 5 C burst tx sequence ? 10.1.30 i/q offset - $75, $76 read ? 10.1.8 i/q output contro l - $5d, $5e write 7.4.12 other modem modes tx preamble in tx mode a transmit preamble feature is provided to aid setup C the preamble may be programmed to any useful repeating 8 - bit pattern.
CMX7163 qam modem CMX7163 ? tx prbs in tx mode, a fixed prbs (pseudo random bit sequence) or a repeated preamble transmission is provided and may be used for test and alignment. a 511 bit prbs conforming to itu - t o.153 (paragraph 2.1) is used to generate the prbs. the output created by transmitting a prbs using 16 - qam is shown in figure 17 . the 16 constellation points are just visible on the plot. figure 17 transmit constellation rx constellation a test mode to examine the rx constellation diagram is also provided, this utilises the ioutputp/n and qoutputp/n pins to produce a diagnostic signal where the rrc filtered i/q signals are output. t his produces a two - dimensional constellation diagram which may be displayed on an oscilloscope in x - y mode. note that best results are often obtained with an analogue oscilloscope. figure 18 constellation diagram C no fre quency or phase error figure 19 constellation diagram C phase error figure 20 constellation diagram C frequency error as shown in the third plot, if there is any frequency error between transmitting and receiving CMX7163 devices then the diagram will spin and be difficult to interpret. therefore other diagnostic modes are provided as described below. any of the gpio signals can be configured to produce a pulse train at the nominal symbol rate of the receiving CMX7163 to aid triggering whilst viewing the constellation diagram (i output or q output alone
CMX7163 qam modem CMX7163 ? vs time) or other diagnostic modes in receive. in some cases it is advisable to obtain a trigger pulse that is synchronised to the transmitting modem symbol rate, for example if the transmitted signal comes from a signal generator. rx diagnostics a diagnostic mode is provided that produces channel filtered i/q signals and an optional dc offset correction indication. this aids in diag nosing reception issues that may be related to i/q dc offsets in the CMX7163 input signal. this diagnostic mode can still be of use when there is a frequency error present in the received signal. as shown in figure 21 and figure 22 , the estimated i/q dc offset correction is an extra dot in the centre of the constellation. figure 21 sample at symbol timing with i/q dc offset di agnostic mode (no frequency error) figure 22 sample at symbol timing with i/q dc offset diagnostic mode (with frequency error) a normalised received constellation diagnostic output is provided. it relies on having detected a fr ame sync and therefore being able to output the signal level measured at the symbol timing instant, with the frequency error removed and amplitude corrected. so long as the CMX7163 remains locked to a suitable signal the normalised constellatio n output will remain static regardless of frequency error and amplitude of the input signal (within limits C see section 9.1.4 CMX7163 fi - 4.x parametric performance ). if the signal becomes noisy or its amplitude small then the constellation points will spread as shown in figure 23 and figure 24 .
CMX7163 qam modem CMX7163 ? figure 23 n ormalised constellation (even with a frequency or phase error) figure 24 normalised constellation (noisy received signal) note: the images of receive diagnostic modes shown above are idealised. in practice when using the i outp ut and q output signals to view diagnostics the transitions between constellation point are not instantaneous. using an analogue oscilloscope is the best way to observe these diagnostic signals. see: ? 10.1.18 modem mode and control - $6b write ? 10.1.10 signal control - $61 write . 7.4.13 data transfer the payload data is transferred to and from t he host via the c - bus command and rx data fifos, each of which provide efficient streaming c - bus access. fifo fill level can be determined by reading the receive fifo level and modem command fifo level and controlled using fifo control - $50 write register. interrupts may be provided on fifo fill thresholds being reached, or successful transfer of a block of host requested fifo data between CMX7163 modem and fifos. each fi fo word is 16 bits, with the least significant byte (lsbyte) containing data, and the most significant (msbyte) containing control information. the control information indicates to the CMX7163 what type, or how mu ch data is in the lsbyte, for example if the byte belongs to a header block or contains only 4 valid bits. the control and data bytes may be written or read together using the receive fifo word and modem command fifo word registers, or individually using t heir byte - wide registers. word wide fifo writes involve writing 16 - bit words to the modem command fifo word register using either a single write or streaming c - bus. the whole word written is put into the command fifo, with the upper byte interpreted as co ntrol and the lower byte as data. this causes the control byte to be held in the command fifo control byte register. byte wide fifo writes involve writing to the modem command fifo data byte register using either single access or streaming c - bus. this cau ses the modem command fifo control byte (msbyte) and data written to the modem command fifo data byte (lsbyte) registers to be put into the command fifo as one word. the control byte can be written separately as a single byte (this does not result in anyth ing being added to the fifo) or is preserved from a previous 16 - bit modem command fifo data byte write. likewise a word read from the rx data fifo will return the receive fifo control byte in the msbyte and the receive fifo data byte at the top of the fif o in the lsbyte. both registers will be updated so that when read next time they will provide details of the next item in the fifo. reading the receive fifo control byte only will not change the fifo content. reading the receive fifo data byte only will pr ovide the data and remove the item from the fifo C updating both control and data registers. in summary: operation effect write modem command fifo control byte register cmd fifo control word updated, nothing added to cmd fifo write modem command fifo da ta byte register cmd fifo control word + data byte written are added to cmd fifo write modem command fifo word register data word (control and data bytes) is added to cmd fifo. cmd fifo control word updated for future writes. read receive fifo control b yte register rx fifo control word is returned, no effect on rx fifo contents
CMX7163 qam modem CMX7163 ? read receive fifo data byte register oldest rx fifo data byte is removed from fifo and returned, rx fifo word updated read receive fifo data word register oldest rx fifo data wo rd (control and data bytes) is removed from fifo and returned, rx fifo control word updated figure 25 command and rx data fifos raw or formatted data may be transmitted with the CMX7163 adding preamble, frame sync and tail bits. raw or formatted transmission/reception is selected using the modem mode and control - $6b write register, each whole transmission/reception must continue in the selected mode. relevant registers are: ? 10.1.18 modem mode and control - $6b write ? 10.1.3 modem command fifo data/control - $48, $49 and $4a write ? 10.1.26 receive fifo data/control - $4c, $4d, $4e read ? 10.1.25 modem command fifo level - $4b read ? 10 .1.27 receive fifo level - $4f read ? 10.1.4 fifo control - $50 write . note: the command fifo and command buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7163 reverting to receive mode. this is to avoid accidentally processing transmit commands pre - loaded by the host as receive commands. this is the only situation in which the fifos or buffers will be flushed other than by direct host instructio n. 7.4.14 data buffering to expand the buffering capabilities of the CMX7163 two internal buffers are provided: a command buffer which buffers commands from the control fifo which are yet to be processed. an rx data buf fer which buffers received data yet to be loaded into the rx data fifo. transfer between the fifos and their respective buffers will occur during transmission, reception and idle mode. such transfer is not instantaneous so the fifo fill levels should be u sed to indicate how much data the host may read or write at any time. the internal buffer fill level - $70 read register allows the buffer fill levels to be read; their contents will be flushed when the respective fifo is flushed. cmd level cmd level 128 x 16 cmd fifo rx level rx level rx fifo level cmd fifo write 8 cmd fifo ctrl cmd fifo write 16 cmd fifo level b i t 1 5 - 8 msb lsb rx fifo read 8 rx fifo read 16 rx fifo ctrl c - bus interface b i t 7 - 0 b i t 1 5 - 8 128 x 16 rx fifo lsb msb mux mux b i t 7 - 0
CMX7163 qam modem CMX7163 ? see: ? 10.1.4 fifo control - $50 write ? 10.1.28 internal buffer fill level - $70 read . note: the command fifo and command buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7163 reverting to receive mode. this is to avoid accidentall y processing transmit commands pre - loaded by the host as receive commands. this is the only situation in which the fifos or buffers will be flushed other than by direct host instruction. 7.4.15 raw data transfer when transferring raw data the fifo control byte in dicates the amount of data that will be transferred in a block before the CMX7163 interrupts the host. byte and bit - wise transfers are possible, providing the facility to transmit or receive a burst of arbitrary l ength, not just a whole number of bytes. it is suggested that data is transferred in the maximum size blocks possible until the end of a burst - where the remaining bits, or bytes can be transferred in a single transaction of the required size. when using byte wise or bit wise transfers the most significant bit of the data byte is transmitted (or received) first. when using bit wise transfers with a bit count of less than 8 the most significant bits are used. in all cases the bits are combined into symbo ls according to the selected modulation type. it is also possible to ignore the concept of blocks of data whilst in raw mode. instead, a transmission can just be treated as a series of bytes to transmit and fifo levels/level irqs used to manage the data f low. likewise in receive the host can request continual data reception and the resulting bytes will be placed in the rx data fifo. fifo levels and level irqs may be used to manage the data flow. this mode provides the ability to simply stream (using stream ing c - bus if desired) multiple bytes into or out of the CMX7163 as fifo content allows. 7.4.16 formatted data transfer when the transfer of formatted data is selected by the modem mode and control - $6b write register the fifo control byte indicates the block type to use in either sending or decoding the data. the block type dictates the format or quantity of data transferred, including how error detection and correction bits are added to the over air data stream. 7.4.17 pre - loading commands it is advisable to pre - load data into the command fifo before transmission begins, or to pre - load receive data commands into the command fifo prior to frame sync reception. 7.4.18 gpio pin operation the CMX7163 provides 4 x gpio pins, each pin can be configured independently as automatic/manual, input/output and rising/falling (with the exception of the combination automatic + input function which is only allowed for gpioa). pins that are automatic outputs become part of a transmit sequence and will automatically switch, along with the ramdac C auxdac1 (if it is configured as automatic) during the course of a burst. pins that are manual are under direct user control. when automatic, a rising, or a falling event at the start or end of transmission will cause the specified gpio to be switched high or low accordingly. gpioa may be configured as an automatic input. this means that any attempted transmission will wait until gpioa input is high (if rising is selected) or low (if falling is selected). see: ? 0 ? p4. 8 : set legacy timing mode ?
CMX7163 qam modem CMX7163 ? b0 adc sample delay 0 - minimal delay mode (gives a delay of 1.2 symbol times) 1 - legacy delay mode (gives a delay of 8.2 symbol times) b1 tx done and tx last tail indication timing 0 - selects minimal jitter of +/ - 0.6 symbol times for tx done and tx last tail indication timing. enables the use of the p4.9 delay adjustment control for tx done and tx last tail indication timing. adjusting these delays enables indication timing to be changed to better match any changes in tx pulse shaping filter delay or for other user purposes. 1 - legacy timing delay mode (delay not specified; delay and jitter behaviours will be consistent so long as the number of data field symbols, number of tai l symbols, and other factors are not changed) b2 - 15 reserved reserved C set to 1 p4. 9 : set tx done delay only if p4.8 b1=0 then this controls the delay in indicating tx done and tx last tail indications, in units of 1.2 symbol times. the default value makes tx done indication coincide with when the end of the last data field symbol analog signal is produced at the cmx7164 ioutput and qoutput pins when the default tx pulse shaping filter is engaged. the user may adjust this parameter value to suit the di fferent delay of any other different pulse shaping filter used. p4. 10 : offset tx end sequence start time adjusts the tx end sequence start time to be earlier than the default time. adjustment is in symbols. ? program block 5 C burst tx sequence ? 10.1.13 gpio control - $64 write ? 10.1.33 gpio input - $79 read . 7.4.19 auxiliary adc operation the inputs to the four auxiliary adcs can be independently routed from any of four dedicated auxadc input pins or the two main inpu ts. auxadcs can be disabled to save power. bias in the vbias con trol - $b7 write register must be enabled for auxiliary adc operation. averaging can be applied to the adc readings by selecting the relevant bits in the auxadc1 - 4 control - $51 to $54 write registers. this is a rolling average system such that a proportion of the current data will be added to the last value. the proportion is determined by the value of the aver age counter in the auxadc1 - 4 control - $51 to $54 write registers. setting the average counter to zero will disable the averager, for an average value of 1; 50% of the current value will be applied, for a value of 2 = 25%, 3 = 12.5%, continuing up to the maximum useful value of 11 = 0.0488%. high and low thresholds may be independently applied to both adc channels (the comparison is applied after averaging, if this is enabled) and an irq generated when an input exce eds the high or low threshold, or on every sample as required. the thresholds are programmed via the auxadc1 - 4 threshold - $55 to $58 write register. auxiliary adc data is read back in the auxadc1 - 4 read - $71 to $7 4 read registers and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). the auxadc sample rate is selected using program block 1 C clock contr ol . see: ? 10.1.5 auxadc1 - 4 control - $51 to $54 write ? 10.1.6 auxadc1 - 4 threshold - $55 to $58 write ? 10.1.29 auxadc1 - 4 read - $71 to $7 4 read ? 10.2.3 program block 1 C clock contr ol
CMX7163 qam modem CMX7163 ? ? 10.1.24 vbias con trol - $b7 write . 7.4.20 auxiliary dac/ramdac operation the four auxiliary dacs are programmed via the auxdac1 - 4 control - $59 to $5c write registers. auxdac1 may also be programmed to operate as a ramdac which will autonomously output a pre - programmed profile at a programmed rate. the ramdac may be configured as automatic or manual using p4. 8 : set legacy timing mode b0 adc sample delay 0 - minimal delay mode (gives a delay of 1.2 symbol times) 1 - legacy delay mode (gives a delay of 8.2 symbol times) b1 tx done and tx last tail indication timing 0 - selects minimal jitter of +/ - 0.6 symbol times for tx done and tx last tail indication timing. enables the use of the p4.9 delay adjustment control for tx done and tx last tail indication timing. adjusting these delays enables indication timing to be changed to better match any changes in tx pulse shaping filter delay or for other user purposes. 1 - legacy timing delay mode (delay not specified; delay and jitter behaviours will be consistent so long as the number of data field symbols, number of tai l symbols, and other factors are not changed) b2 - 15 reserved reserved C p4. 9 : set tx done delay only if p4.8 b1=0 then this controls the delay in indicating tx done and tx last tail indications, in units of 1.2 symbol times. the default value makes tx done indication coincide with when the end of the last data field symbol analog signal is produced at the cmx7164 ioutput and qoutput pins when the default tx pulse shaping filter is engaged. the user may adjust this parameter value to suit the di fferent delay of any other different pulse shaping filter used. p4. 10 : offset tx end sequence start time adjusts the tx end sequence start time to be earlier than the default time. adjustment is in symbols. program block 5 C burst tx sequence . the auxdac1 - 4 control - $59 to $5c write register, with b12 set, controls the ramdac mode of operation when configured as a manually triggered ramdac. the ramdac ramp rate is controlled by the internal system clock rate , which changes between active cs/tx/rx modes and idle mode. therefore it is inadvisable to return to idle mode prior to ramdac ramp completion. the default profile is a raised cosine (see table 7 in the user manua l), but this may be over - written with a user defined profile by writing to program block 0. the current profile may be scaled using the signal control - $61 write register. the auxda c outputs hold the user - program med level during a powersave operation if left enabled, otherwise they will return to zero. see: ? 10.1.7 auxdac1 - 4 control - $59 to $5c write ? 10.2.2 program block 0 C ramdac ? 10.2.3 program block 1 C clock contr ol ? 0 ? p4. 8 : set legacy timing mode ?
CMX7163 qam modem CMX7163 ? b0 adc sample delay 0 - minimal delay mode (gives a delay of 1.2 symbol times) 1 - legacy delay mode (gives a delay of 8.2 symbol times) b1 tx done and tx last tail indication timing 0 - selects minimal jitter of +/ - 0.6 symbol times for tx done and tx last tail indication timing. enables the use of the p4.9 delay adjustment control for tx done and tx last tail indication timing. adjusting these delays enables indication timing to be changed to better match any changes in tx pulse shaping filter delay or for other user purposes. 1 - legacy timing delay mode (delay not specified; delay and jitter behaviours will be consistent so long as the number of data field symbols, number of tai l symbols, and other factors are not changed) b2 - 15 reserved reserved C set to 1 p4. 9 : set tx done delay only if p4.8 b1=0 then this controls the delay in indicating tx done and tx last tail indications, in units of 1.2 symbol times. the default value makes tx done indication coincide with when the end of the last data field symbol analog signal is produced at the cmx7164 ioutput and qoutput pins when the default tx pulse shaping filter is engaged. the user may adjust this parameter value to suit the di fferent delay of any other different pulse shaping filter used. p4. 10 : offset tx end sequence start time adjusts the tx end sequence start time to be earlier than the default time. adjustment is in symbols. ? program block 5 C burst tx sequence ? 10.1.10 signal control - $61 write . 7.4.21 spi thru - port the CMX7163 offers an spi thru - port which allows the host, using the main c - bus interface, to command the CMX7163 to read or write up to three external spi/c - bus devices attached to the CMX7163 . the CMX7163 acts as a spi/c - bus master in th is mode, controlling three chip selects, clock and data out (mosi), and receiving data in (miso). each individual spi/c - bus device can be independently configured using program block 6 C spi thru - port configuration to have clock speed, inter - frame guard period and clock phase/polarity to match the specification of the slave spi/c - bus device attached. in order to offer a simpler, more convenient interface, a device can be designated c - bus, rather than spi. this mean s that data read/written is assumed to be in the format: address byte, data byte1 (optional), data byte 2 (optional) in each case the CMX7163 , as the master, drives the address and data for a write operation, o r drives the address and receives the data for a read operation. commands can be called 0, 1 or 2 byte reads or writes C with a 0 byte write typically being a reset command. as the word format is known, then for convenience only the desired read data is re turned to the host. spi mode is a little more flexible. no assumption is made about the spi word format, nor any assumption that the length is a whole number of bytes. see: ? 10.1.11 spi thru - port control - $62 write ? 10.1.12 spi thru - port write - $63 write ? 10.1.32 spi thru - port read - $78 read ? 10.2.8 program block 6 C spi thru - port configuration .
CMX7163 qam modem CMX7163 ? 7.4.22 spi/c - bus agc using the spi thru - port, the CMX7163 provides a method of controlling an external c - bus device capable of implementing variable gain steps. when using i/q receive modes this allows for a fast response to large signals causing clipping and an increase in gain when the s ignal becomes too small. controlling the external device requires the host to program a table of eight c - bus commands that the CMX7163 stores and outputs when a specific gain step is required. the commands may be produced by the agc function, or the CMX7163 can be commanded to output them manually if required. commands are programmed using program block 7 C agc configuration . agc i s controlled by sensing clipping in the received signal C in which case the gain is backed off. while searching for a frame sync the gain will also be backed off when the signal is considered large C this ensures that after frame sync is detected there i s headroom for the amplitude to increase a little. if the signal is sensed to be small for a period of time the gain can also be increased. the threshold for what is considered a small (or large) signal - requiring a gain change, the time for which it shou ld remain small and the time to allow a gain adjustment to take effect is programmable. the overall system is shown below: figure 26 agc using spi thru - port controlling the external device as shown in figure 26 causes the gain to step suddenly. this in itself may cause a short burst of errors, so once signal is being received it may be desirable to ensure that the gain is not changed unnecessarily. this is typi cally the case with short bursts of data, where it is likely that the signal amplitude will remain constant throughout the burst. to help achieve this, various agc automatic modes are provided: o manual gain C controlled manually always, allowing user contr ol and for control during latching in of i/q dc corrections o full auto C gain can increase and decrease during the search for frame sync and during burst reception o agc lock on fs C gain can increase and decrease during the search for frame sync but once a f rame sync is detected its level will be fixed o agc down after fs C gain can increase and decrease during the search for frame sync but once a frame sync is detected its level will only decrease. agc changes during the frame sync can cause the frame sync to be corrupted and therefore not detected by the CMX7163 . to avoid this problem the CMX7163 compares the incoming on - channel signal to a signal detect threshold, the resu lting agc behaviour is as shown in figure 27 : cmx 7163 host up t / r i input q input local oscillator ( if ) local oscillator ( quadrature ) spi thru - port clip / level sense agc gain step select c - bus control of external device rf receiver ic c - bus control registers lna gain control register baseband gain control register
CMX7163 qam modem CMX7163 ? figure 27 agc behaviour during burst reception a general issue with i/q receivers is that of dc offsets. offsets are generated by the receiver hardware and typically vary with channel selection, but depending on receiver architecture can also change with gain. the CMX7163 is capable of calculating i/q dc offset corrections but, if the gai n steps suddenly and therefore the dc offset changes suddenly, errors may occur. once again this may only be an issue for longer bursts when it is necessary to change gain during reception. to overcome the dc offset issue the CMX7163 allows an i/q dc offset correction to be latched in for each agc gain step. when a gain step other than maximum gain is selected the tabulated dc offset correction will become active and tracking will be suspended. additionally, in re ceivers with large dc offsets present, a gain change may result in a sufficiently large step in dc offset that the signal will look small/large to the agc algorithm resulting in unwanted gain changes. the CMX7163 is able to use the i/q dc offset information to correct for this effect. agc thresholds and parameters may be changed during reception for ease of setup and are controlled using the signal control - $61 write register. all times are measured in un its of 6/5 of a symbol period. all levels or thresholds are compared to the magnitude of signed 16 bit samples, with max range therefore being 32767 to - 32768. see: ? 10.2.8 program block 6 C spi thru - port configuration ? 10.2.9 program block 7 C agc configuration ? 10.1.14 agc control - $65 write ? 10.1.10 signal control - $61 write ? 11.2.1 effect of agc on dc offsets . preamble frame sync data payload timer starts to count down when detect threshold is met clip threshold high threshold detect threshold if ( timer > allow high time ) and ( signal > high threshold ) then backoff no backoff even if signal > high threshold timer expires : either framesync detected ( so agc behaves based on full auto / lock on fs or agc down after fs selection ) or a false detect , so continue running agc normally normal agc operation C reacts to small signals by increasing gain , clipping and large signals result in decreasing gain
CMX7163 qam modem CMX7163 ? 7.5 digital system clock generators the CMX7163 includes a two - pin xtal oscillator circuit. this can either be configured as an oscillator, as shown in section 4 , or the xtal/clk input can be driven by an externally generated clock. the crystal (xtal) source frequency is typically 9.6mhz and if an external oscillator is used the input frequency is typically 9.6 or 19.2 mhz. for both cases reference frequ encies in the range specified in 9.1.2 operating limits may be used. 7.5.1 main clock operation a digital pll is used to create the main clock for the internal sections of the CMX7163 . the configuration of the main clock and the internal clocks derived from it is controlled using program block 1 C clock contr ol . the CMX7163 defaults to settings appropriate for a 19.2mhz externally generated clock with a baud rate of 9600s/s, however if a different reference frequency is to be used, or a different baud rate required, then program block entries p1.1 to p1 .6 will need to be programmed appropriately at power - on. a table of preferred values is provided in table 8 along with details of how to calculate settings for other baud rates and crystal frequencies. figure 28 main clock generation see: ? 10.2.3 program block 1 C clock contr ol 1 to 4096 ph det q pump vco lock timer 1 to 512 loop filt ref clk vco clk symbol clock main pll internal system clk prog reg p 1 . 1 ( idle ) , p 1 . 4 ( active ) pll clkin ( xtal ) pll clkout symbol clock divider 1 to 256 internal clk divider 1 to 64 prog reg p 1 . 5 aux adc clk divider 3 to 1024 aux adc clock prog reg p 1 . 0 prog reg p 1 . 2 ( bits 8 - 0 ) prog reg p 1 . 3 5 main pll out tx / rx ( active ) ( idle )
CMX7163 qam modem CMX7163 ? 7.5.2 system clock operation two system clock outputs , sysclk1 and sysclk2, are available to drive additional circuits, as required. the system clock circuitry is shown in figure 29 digital system clock generation schemes . having chosen the input frequency source, s ystem clock generation may be by simply dividing the input frequency source, or via its own phase locked loop. the system clock pll does not affect any other internal operation of the CMX7163 - so if a frequency t hat is not a simple fraction of the xtal is required, it can be used with no side effects. there is one phase locked loop, with independent output dividers to provide phase locked output signals . figure 29 digital system clock generation schemes see: ? 10.2.3 program block 1 C clock contr ol . 1 to 4096 ph det q pump 1 or 2 vco 1 to 512 loop filt syspllcon 0 syspllcon 1 syspllcon 2 ref clk vco clk local clk sysclk 1 sysclk pll sysclk 2 sysclkdiv 2 b 15 , 13 , 5 - 0 sysclkcon b 1 - 0 sysclkin ( xtal ) pll clkin pll clkout sysclk 1 divider 1 to 64 sysclk 2 divider 1 to 64 1 2 0 1 2 0 1 0 sysclkcon b 3 - 2 sysclkcon b 5 - 4 phase shift 0 1 sysclkdiv 1 b 12 sysclkdiv 1 b 15 , 13 , 5 - 0 sysclkdiv 1 b 11 - 6 lock timer
CMX7163 qam modem CMX7163 ? 7.6 signal level optimisation the internal signal processing of the CMX7163 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits. for a device working from a 3.3v supply, the sign al range which can be accommodated without distortion is specified in 9.1.3 operating characteristics . signal gain and dc offset can be manipulated as follows: 7.6.1 transmit path levels for the maximum signal out of the i/q outputs, the signal level at the output of the modem block is set to be 0db, the fine output adjustment has a maximum attenuation of 6db and no gain, whereas the coarse output adjustment has a variable att enuation of up to 14.2db and 6db gain. the signals output from i output and q output may be independently inverted. inversion is achieved by selecting a negative value for the (linear) fine output adjustment. when transmitting i/q format signals inverting one of the i/q pair has a similar effect to swapping i with q. dc offsets may be added to the signal, however care must be taken that the combination of gain and dc offset does not cause the signal to clip at any point in the signal processing chain, which is: fine gain followed by dc offset addition, followed by coarse gain. see: ? 10.1.8 i/q output contro l - $5d, $5e write ? 10.1.23 i/q output coarse gain - $b4, $b5 write . 7.6.2 receive path levels the coarse input has a variable gain of up to +22.4db and no attenuation. with the lowest gain setting (0db), the maximum allowable input signal lev el at the i input or q input pins is specified in section 9.1.3 operating characteristics . a fine input level adjustment is provided, although the CMX7163 should operate correctly with the default level selected. the primary purpose of the fine input level adjustment is to allow independent inversion of the i/q input signals. inversion is achieved by selecting a negative value fo r the (linear) fine input gain adjustment. when receiving i/q format signals inverting one of the i/q pair has a similar effect to swapping i with q. dc offsets can be removed by the CMX7163 , the offset to remove can be selected by the host or calculated automatically by the CMX7163 . it should be noted that if the maximum allowable signal input level is exceeded, signal distortion will occur regardless of the internal dc o ffset removal or attenuation. see: ? 10.1.9 i/q input control - $5f, $60 write ? 10.1.20 i/q input configuration - $b0 write .
CMX7163 qam modem CMX7163 ? 7.7 c - bus register summary table 2 c - bus registers addr. (hex) read/ write register word size (bits) $01 w c - bus general reset 0 $48 w modem command fifo data byte 8 $49 w modem command fifo word 16 $4a w modem command fifo control byte 8 $4b r modem comma nd fifo level 8 $4c r receive fifo data byte 8 $4d r receive fifo word 16 $4e r receive fifo control byte 8 $4f r receive fifo level 8 $50 w fifo control 16 $51 to $54 w auxadc1 - 4 control 16 $55 to $58 w auxadc1 - 4 thr eshold 16 $59 to $5c w auxdac1 - 4 control 16 $71 to $74 r auxadc1 - 4 read 16 $5d w i output control 16 $5e w q ou tput control 16 $5f w i input control 16 $60 w q input control 16 $61 w signal control 16 $65 w agc control 16 $66 w rx tracking 16 $69 w reg done select 16 $70 r internal buffer fill level 16 $75 r i offse t 16 $76 r q offset 16 $77 r agc gain and rssi 16 $7a r rx error magnitude 16 $7b r frequency error 16 $62 w spi thru - port control 16 $63 w spi thru - port write 16 $64 w gpio control 16 $78 r spi thru - port read 16 $79 r gpio input 16 $6a w programming 16 $6b w modem mode and control 16 $6c w irq mask 16 $7d r programming register read 16 $7e r irq status 16 $7f r modem mode and control readback 16 $b0 w i/q input configuration 16 $b1 w i input coarse gain 16 $b2 w q input coarse gain 16 $b3 w i/q output configuration 16 $b4 w i output coarse gain 16 $b5 w q output coarse gain 16 $b7 w vbias control 16 all other c - bus add resses are reserved and must not be accessed.
CMX7163 qam modem CMX7163 ? 8 CMX7163 fi - 4.x features the CMX7163 fi - 4.x uses a qam modulation scheme, switchable between 4 - , 16 - and 64 - qam on a burst by bu rst basis. the symbol rate is configurable up to 20,000 symbols/sec resulting in 106,000 user bits per second maximum. raw data can be transferred, in addition to formatted data blocks. formatted data blocks may be of variable length C from 15 to 416 bytes and support a combination of 16 - bit or 32 - bit crc for error detection, plus error correction. 8.1 CMX7163 fi - 4.x modulation CMX7163 fi - 4.x produces qam modulation, with three opt ions: 4 - , 16 - or 64 - qam, see figure 30 . in each case, the signal is root raised cosine filtered. the same filter is applied in receive to remove inter - symbol interference. due to the way the signal is produced, the re is no deviation to select, instead only the baud rate may be altered. this has a direct effect on the signal bandwidth. a baud rate of 18ksymbols/second is typical of a 25khz channel spacing and provides: qam variant bits per symbol base over - air bit r ate (18,000symbols/s) raw mode over - air bit rate (18,000symbols/s) 4 - qam 2 36,000bps 32,000bps 16 - qam 4 72,000bps 64,000bps 64 - qam 6 108,000bps 96,000bps figure 30 qam mappings the signal spectr um is identical in bandwidth when using 4 - , 16 - or 64 - qam, however the peak - to - mean of each modulation type does vary. 4 - qam has a peak to mean of 5.3db ( ? =0.2) or 3.8db ( ? =0.35) 16 - qam has a peak to mean of 7.8db ( ? =0.2) or 6.4db ( ? =0.35) 64 - qam has a peak to mean of 9db ( ? =0.2) or 7.5db ( ? =0.35) the difference between the base over air rate and the raw mode rate (which is the actual user data rate in raw mode at 18ksymbols/second) is due to some symbols being used internally by the modem to perfor m channel equalisation. a further implication of this is that any transmission must contain a multiple of 16 symbols, the CMX7163 will automatically pad as necessary. 01 00 10 11 0110 0100 0111 0101 0011 0001 0010 0000 1001 1011 1000 1010 1100 1110 1101 1111 4 - qam mapping 16 - qam mapping 000101 000100 000111 000110 001111 001110 001101 001100 001010 001011 001000 001001 000000 000001 000010 000011 64 - qam mapping 101101 101100 101111 101110 100111 100110 100101 100100 100010 100011 100000 100001 101000 101001 101010 101011 010001 010000 010011 010010 011011 011010 011001 011000 011110 011111 011100 011101 010100 010101 010110 010111 111001 111000 111011 111010 110011 110010 110001 110000 110110 110111 110100 110101 111100 111101 111110 111111
CMX7163 qam modem CMX7163 ? 8.2 CMX7163 fi - 4.x radio inter face qam modulation requires control of both phase and amplitude in the transmitter, and to measure both phase and amplitude in the receiver. therefore the CMX7163 fi - 4.x offers i/q transmit and i/q receive interfaces. this is shown in figure 31 , using the cmx992 3 for reception and the cmx998 4 for transmit C with rf power amplifier linearisation. the internal functions of the CMX7163 when operating in this mode are shown in figure 2 . figure 31 outline radio design (i/q in/out for qam) use of i/q receive mode brings wi th it the problem of i/q dc offsets. there are dc offsets caused by the radio receiver C resulting in the signal into the CMX7163 having a dc offset other than bias. the offset needs to be removed prior to demodu lation. offsets typically remain constant for a particular radio frequency selected, but will vary if that frequency is changed. gain within the radio receiver may also affect the dc offset seen by the CMX7163 . i/q dc offset effects are a radio issue which is beyond the control of the CMX7163 . however the CMX7163 does provide dc offset calculation and removal. these are descri bed in detail in the application note section 11.2 dc offsets in i/q receivers . 8.2.1 control interfaces as can be seen in figure 31 , the CMX7163 provides control interfaces to assist with controlling the radio transmitter and receiver. these include: ? a spi thru - port C port which may be used to control radio ics with c - bus/spi interfaces ? a ra mdac which can be used to control pa ramp up and ramp down ? four gpio pins which may be used for tx/rx switching, lna off and general device control 3 cmx992 is an rf quadrature/if receiver 4 cmx998 is a cartesian feedback loop transmitter cmx 7163 host p power amplifier tx / rx i output i input q input lna local oscillator ramdac ( aux dac 0 ) pa gain control 2 x adc lo cmx 992 2 x dac thru c - bus 4 lna enable c - bus gpio gpion 90 90 q output directional coupler local oscillator cmx 998 2 2 2 2
CMX7163 qam modem CMX7163 ? 8.3 CMX7163 fi - 4.x formatted data the CMX7163 fi - 4.x supports formatted data, which provides the ability to channel code blocks of data using a variety of coding rates and crcs. a frame structure would typically consist of a 24 - symbol frame sync pattern followed by a 'header block', one or more 'intermediate blocks and a 'last block'. the 'header' block is self - contained in that it includes its own checksum (crc1), and would normally carry information such as the address of the calling and called parties, the number of following blocks i n the frame (if any) and miscellaneous control information. the 'intermediate' block(s) contain only data, the checksum at the end of the 'last' block (crc2) also checks the data in any preceding 'intermediate' blocks. this checksum calculation should be r eset as required using the reset crc2 block type C so that any transmitted crc2 contains the crc of only the desired blocks. in receive it must be reset to match the expected input data block sequence. a variety of different frame formats are possible, s ome examples are illustrated in figure 32 . figure 32 suggested frame structures the CMX7163 performs all of the bloc k formatting and de - formatting. when receiving header blocks and last blocks the CMX7163 will indicate crc success or failure and will provide the data regardless. the size of the data block can be varied, as can the coding rate applied. a lower coding rate (more fec bits) will improve performance in noisy or faded conditions but will reduce the user data rate available. small data blocks provide the ability to produce a short burst or granularity in burst size. h owever to cope with fading conditions longer coded blocks are necessary. the CMX7163 fi - 4.x provides blocks with the following formatted block sizes/rates: table 3 format ted block types, sizes and rates user(crc) bytes for a: block type block size coding rate (4 - /16 - qam) coding rate (64 - qam) header block inter block last block 0 15 bytes 0.75 0.83 13(2) 15 11(4) 1 60 bytes 0.75 0.83 58(2) 60 56(4) 2 33 bytes 0.55 0 .61 31(2) 33 29(4) 3 37 bytes 0.62 0.69 35(2) 37 33(4) 4 44 bytes 0.55 0.61 42(2) 44 40(4) 5 176 bytes 0.55 0.61 174(2) 176 172(4) 6 73 bytes 0.52 0.58 71(2) 73 69(4) 7 292 bytes 0.52 0.58 290(2) 292 288(4) 8 88 bytes 0.55 0.61 86(2) 88 84(4) 9 352 bytes 0.55 0.61 350(2) 352 348(4) 10 104 bytes 0.65 0.72 102(2) 104 100(4) 11 416 bytes 0.65 0.72 414(2) 416 412(4) header block normal frame
CMX7163 qam modem CMX7163 ? 8.4 receiver response equaliser when receiving signals using a radio receiver the signal provided to the CMX7163 is likely to be distorted. considering the architecture of figure 31 as typical, the distortion will largely be caused by the crystal filter C shown as a bandpass filter in the diagram. the crystal filter operates on the receiv ed signal at an intermediate frequency. i ts purpose is to attenuate unwanted signals , such as those on adjacent channels , before they get to the CMX7163 . 5 typically the pass - band of the crystal filter is not flat or perfectly linear phase, res ulting in the wanted qam signal being distorted due to the amplitude/phase response of the fil ter. the result is usually a significantly degraded receive signal and therefore poor receive performance. other radio arc hitectures may provide baseband filteri ng in order to help reject unwanted adjacent channel sign als. such filtering may also have a pass - band that is not flat, and therefore will degrade reception. the CMX7163 provides a receiver response equaliser that will compensate for the grou p delay and variation in gain of the crystal filter, or any other distortions p resent in the received signal. the equaliser must be trained with a clean, high level 4 - qam signal in order to establish the receiver response and produce a fi lter which compens ates for it. once this filter is ca lculated it may be read from the CMX7163 and stored for later use. the CMX7163 can be configured with up to two previously stored receiver response equaliser filters which may, for example , be used to compensate for two different crystal filters in a radio designed to receive in two channel bandwidths. although trained using a 4 - qam signal , the resulting filter is suitable to compensate for the receiver response whilst rece iving 4, 16 or 64 - qam sig nals. a suitable training signal may either be produced using another CMX7163 or by using the training sequence described in section 11.8 receiver response equaliser training sequence . the receiver response equaliser has two modes, single mode produces better results when correcting for receiv ers with a simple baseband roll off (for example in a direct conversion architecture) ; d ual mode produces better resul ts when compensating for a radio receiver which includes a crystal filter. prog ram block 11 C receiver response equaliser provides equaliser mode selection, allows adjustment of the gain used in the feedback path wh en training the equaliser and allows th e training time to be altered. the same program block allows the filter resulting from training to b e read for storage and to b e programmed back into the CMX7163 later , for use when receiving. an example of the effect of the receiver crystal filter on a 4 and 16 - qam signals is shown in figure 33 . once the equaliser has been trained , the resulting received signal i s as shown in figure 34 . each plot is gathered by using the rx diagnostics mode of the CMX7163 , see section 7.4.12 other modem modes for details. 5 note that the CMX7163 provides significant channel filtering itself, but further r ejection of unwanted signals is desirable in most applications to improve receiver dynamic range and prevent blocking or products generating intermodulation products reaching the low power back - end of the receiver.
CMX7163 qam modem CMX7163 ? figure 33 received 4 and 16 - qam signals, no equalisation figure 34 received 4 and 16 - qam signals with equalisation results when using the receiver response equaliser are shown in section 8.6.4 receiver response equaliser performance . see: ? 10.1.18 modem mode and control - $6b write ? 10.2.12 prog ram block 11 C receiver response equaliser ? 11.8 receiver response equaliser training sequence
CMX7163 qam modem CMX7163 ? 8.5 CMX7163 fi - 4.x typical transmit performance the CMX7163 fi - 4.x transmits qam modulation using an i/q interface. the modulation may be evaluated using a test system as illustrated in figure 35 tx spectrum and modulation measurement configuration for i/q operation . figure 35 tx spectrum and modulation measurement configuration for i/q operation some typical results are shown in the follo wing figures. the internal prbs generator was used to generate the data in all the results shown. two baud rates are demonstrated C 18k symbols/second which is typical of a 25khz channel and 9k symbols/second which is typical of a 12.5khz channel. in all c ases the transmit filter selected had ? =0.2. depending on transmitter requirements (e.g. applicable standards) faster baud rates may be possible. cmx 7163 cmx 998 transmitter board spectrum analyser / vector signal analyser i / q inputs i output q output
CMX7163 qam modem CMX7163 ? 4 - qam modulation spectrum with 18k symbols/second adjacent channel measurement for 25 khz channel: acp = - 76db (integration window = 16khz) constellation diagram (receiver filtered) error vector figure 36 tx modulation spectra (4 - qam), 18ksymbols/sec i/q modulation i nto cmx998
CMX7163 qam modem CMX7163 ? 16 - qam modulation spectrum with 18k symbols/second adjacent channel measurement for 25khz channel: acp = - 75db (integration window = 16khz) constellation diagram (receiver fil tered) error vector figure 37 tx modulation spectra (16 - qam), 18ksymbols/sec i/q modulation into cmx998
CMX7163 qam modem CMX7163 ? 64 - qam modulation spectrum with 18k symbols/second adjacent channel measurement for 25khz channel: acp = - 75db (integration window = 16khz) figure 38 tx modulation spectra (64 - qam), 18ksymbols/sec i/q modulation into cmx998 for a particular baud rate we can see that the spectral shape, and adjacent channel power measureme nts for each qam type are almost identical. this is to be expected, as each is generated using the same filters. the average power generated will vary though, as each type of qam used has a different peak C to - mean ratio C and the CMX7163 transmits each with the same peak power.
CMX7163 qam modem CMX7163 ? 16 - qam modulation spectrum with 9k symbols/second adjacent channel measurement for 12.5khz channel: acp = - 76db (integration window = 8khz) constellation diagram (receiver filtered) error vector figure 39 tx modulation spectra (16 - qam), 9k symbols/sec i/q modulation into cmx998 comparing figure 37 an d figure 39 demonstrates that changing baud rate simply scales the transmitted spectrum C halving baud rate will halve the bandwidth occupied. this relationship can be used to select the maximum baud rate for a giv en channel bandwidth.
CMX7163 qam modem CMX7163 ? 8.6 CMX7163 fi - 4.x typical receive performance 8.6.1 signal to noise and co - channel the performance of the CMX7163 fi - 4.x when receiving is shown in the followin g graphs. it should be noted that error rate performance depends on the modulation rate; whether 4 - qam, 16 - qam or 64 - qam is in use; the coding type selected and the block size. the CMX7163 fi - 4.x supports multiple combinations of these factors and it is beyond the scope of this document to provide data for every combination, however graphs are provided showing a selection of representative cases ranging from best case performance (maximum coding and block size) to worst case where no coding is used (raw mode). formatted block types 0, 6 and 7 (see table 3 and section 8.3 CMX7163 fi - 4.x formatted data , for details) show different levels of error correction performance, formatted block type 7 giving the best performance (see table 3 ). in all of the following graphs ( figure 40 - figure 47 ) the data rate is 18 ksymbols/s, which is typical of the rate that may be achieved in a 25khz rf channel. the selected transmit and receive filters had ? =0.2. the si gnal to noise ratio is calculated as: snr = mean signal power - 174 + nf + 10 log 10 (rxbw) where: nf = receiver noise figure in db rxbw = receiver noise bandwidth, which in figure 40 - figure 47 is 18khz mean signal power is in dbm snr = signal to noise ratio in db figure 40 modem sensitivity performance the co - channel rejection ratio ( figure 41 ) is measured with an interferer modulated with 400hz fm and having a deviation of 3khz; which is 12% of the nominal 25khz channel bandwidth. this particular interfering signal is used as it is specified in etsi standard en 300 113 for co - channel tests. the measurement is taken at approximately 20db above sensitivity and although this is not in line with
CMX7163 qam modem CMX7163 ? en 300 113 - it means that the data presented here gives a true representation of the performance of the CMX7163 fi - 4.x modem rather than being partially influenced by the thermal noise level. the methodology is in line with standards for 6.25khz channel spaced systems (en 301 166). figure 41 modem co - c hannel rejection with fm interferer (as en 300 113) figure 42 4 - qam performance with different coding schemes
CMX7163 qam modem CMX7163 ? figure 43 16 - qam performance with d ifferent coding schemes figure 44 64 - qam performance with different coding schemes the required performance of a modem may be assessed in terms of either bit error rate (ber) or packet error rate (per ). the performance of both measures is affected by coding type and block size but the per also depends on the size of the packet. short packets with strong coding will exhibit a much lower
CMX7163 qam modem CMX7163 ? per then a long packet with no coding. a comparison of per vs ber f or 4 - qam modulation is shown in figure 45 based on packets of 182 bytes. the same comparisons for 16 - qam and 64 - qam are shown in figure 46 and figure 47 respectively. regulatory standards for radio modem designs using the CMX7163 fi - 4.x commonly use either ber or per to assess the receiver performance. typical ber assessm ent values are 5%, 1% or 0.1% whereas per is most often assessed at 20%. it will be observed from figure 45 that a 4 - qam modem using no coding (raw mode) with 182 - byte packets will achieve 20% per at just over 13db snr while 1% ber is achieved at 9.5db snr. with formatted block type 6 (see table 3 ), approximately 7db snr gives 1% ber and 20% per. it is recommended that designers assess the performance of the CMX7163 fi - 4.x with the correct bit rate, coding, packet size etc. for their particular application having in mind the regulatory requirements that may apply and paying careful attention to the test methods th at will be used. figure 45 comparison of ber and per for 4 - qam modulation
CMX7163 qam modem CMX7163 ? figure 46 comparison of ber and per for 16 - qam modulation figure 47 comparison of ber and per for 64 - qam modulation 8.6.2 adjacent channel the CMX7163 fi - 4.x provides excellent rejection of adjacent signals presen t on the i/q inputs. assessment of the adjacent channel rejection (acr) performance of the modem is normally made in terms of ber or per for a given ratio between the wanted signal (on channel) and larger interferer on the adjacent channel. detailed measur ement methods vary depending on the standards in use, in particular whether the wanted signal is raised above the sensitivity limit and where the reference is taken. the figures quoted here are based on the measurement method from en 300 113, which tends t o give lower
CMX7163 qam modem CMX7163 ? figures than some other methods. in these tests the adjacent channel signal is close to the maximum input signal amplitude allowed by the CMX7163 fi - 4.x . the figures quoted in table 4 are based on the difference between the interferer (400hz fm modulation, 3khz deviation) and the mean power of the wanted signal for less than 20% per (182 byte packets), for 18 ksymbols/s. it has been observed that adjacent channel rejection is limited by the headroom offered by the i/q inputs above the sensitivity level of the input signal. this means that when the adjacent channel interferer reaches the maximum allowed input level of the i/q inputs, a rapid t ransition from almost zero ber to a large ber is observed. given the relative sensitivity levels of the 4 - qam, 16 - qam and 64 - qam signals the result is a measured adjacent channel rejection of: table 4 acr rejection performance 4 - q am 16 - qam 64 - qam raw data 62db (less than 1e - 3 ber) 55db (less than 1e - 3 ber) 48db (less than 1e - 3 ber) formatted block type 0 65db for 6% per 62db (0% per) 58db (19% per) formatted block type 6 65db for 0% per 62db (0% per) 58db (0% per) formatted blo ck type 7 65db for 0% per 62db (0% per) 58db (0% per) the figures in table 4 are typical of what may be achieved with CMX7163 fi - 4.x and a typical i/q radio receiver with no adjacent channel selectivity in the radio circuits. in a more normal rf architecture some adjacent channel selectivity will be provided making system results better than the measured values for the CMX7163 fi - 4.x alone. furthermore, the results observed are not necessarily the maximum that the CMX7163 can achieve but are limited by the practical dynamic range of the CMX7163 combined with the system gain and noise figure of the receiver used in these tests. 8.6.3 receiver dynamic range the adjacent channel rejection results in section 8.6.2 also indicate that a wanted signal can be successfully received over the dynamic range stated in table 4 without any need for an agc. note that this is limited at the top end by the maximum allowed signal amplitude into the CMX7163 , but performance at the bottom end is affected by noise added by the test receiver C so these figures are not the absolute limit of CMX7163 fi - 4.x performance. 8.6.4 receiver response equaliser performance the performance of the CMX7163 when receiving a signal through a typical if crystal filter as used in ev9910b/ev9920b 6 is shown in the following graphs. the nominal bandwidth of the filter is 15khz, however its response within that bandwidth is not flat, both amplitude and group delay distortion is in troduced into the signal. the followi ng tests were carried out using a 16 ksymbols/s 4 - qam, 16 - qam or 64 - qam signal. where the results are quoted as using no equalisation the receiver response equaliser was disabled. where the results are quoted as equali sed the receiver response equaliser was provided with a 4 - qam training sequence of level C 70dbm which produced 400mv (differential) on the i and q inputs. equaliser gain was set to 3000 and training lasted for 800 symbol periods. while training the receive d signal had le ss than 100hz frequency error. once trained the resulting equaliser coefficients were used for the remaining tests. firstly the signal to noise performance of equalised and non equalised received signals are compared. the test is similar to that described in 8.6.1 signal to noise and co - channel , except that as the baud rate is 16 ksymbols/ s the rxbw parameter is 16000. applying this factor also means that the results in section 8.6.1 may be directly compared to those below in figure 48 . 6 evaluation card for cmx991 / cmx992 r f quadrature transceiver / receiver ics.
CMX7163 qam modem CMX7163 ? figure 48 4 - qam signal to noi se performance, equalised and not equalised figure 49 16 - qam signal to noise performance, equalised and not equalised
CMX7163 qam modem CMX7163 ? figure 50 64 - qam signal t o noise performance, equalised figure 48 , figure 49 and figure 50 show that equaliser training improves the received signal performance in all cases: 4 - qam, 16 - qam and 64 - qam. we can see that without equalisation 16 - qam signals have a residual bit error rat e even with a high signal level , as the non equalised curve flattens off . 64 - qam is unusable without equalisation, producing a residual bit error rate of greater than 1e - 2 reg ard less of signal to noise ratio. this is not plotted in figure 50 . the 4 - qam curves show that 4 - qam is less affected by the receiver response, therefore the improvement made by equalisation is less. once equalisation is present t he measured figures compare well to the results (with no crystal filter in the receive path) in section 8.6.1 signal to noise and co - channel . the response of crystal filters va ries with temperature. t his will affect the ability of an equaliser which is trained at room temperature to compensate effectively for filter distortio ns at a different temperature. measurements showing the degradation in signal to noise performance over temperature when the equa liser was trained at room temperature are shown in figure 51 .
CMX7163 qam modem CMX7163 ? figure 51 performance of 16 - qam equalised signals with temperature variation equaliser performanc e with temperature variation was measured by calibrating the receiver response equaliser at room te mperature. tests were carried out using 16 - qam modulation with a signal level of - 103dbm ( figure 51 ) and a signal l evel of C 95dbm f or 64 - qam ( figure 52 ), in both cases using the ev9910b 7 . ber performance was measured with and without equalisation being applied then the temperature was varied and the equalised and non - equalised bit err or rate measurements repeated. the results are shown in figure 51 and figure 52 . the results show that equalisation is most effective at the temperature at which ca libration was carried out and that performance degrades outside of this temperature. for all results a frequency error between transmitter and receiver of less than 100hz magnitude was observed. as t he crystal filter was that used in the ev9910b/ev9920b , it should be noted that its specified range of operation is - 20 to +55 deg c . it was also observed that a re - calibration at a given temperature would result in equalisation coefficients capable of producing a much improved ber at that temperature. figure 52 performance of 64 - qam equalised signals with temperature variation 7 evaluation card for cmx991 / cmx992 rf quadrature transceiver / receiver ics.
CMX7163 qam modem CMX7163 ? 9 performance specification 9.1 electrical performance 9.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units power supplies dv dd - dv ss - 0.3 4.0 v dv core - dv ss - 0.3 2.16 v av dd - av ss - 0.3 4.0 v voltage on any pin to v ss - 0.3 iov dd + 0.3 v voltage differential between power supplies: dv dd and av dd 0 0.3 v dv ss and av ss 0 50 mv l9 package (64 - pin lqfp) min. max. units total allowable power dissipation at tamb = 25oc 1690 mw ... derating 16.9 mw/oc storage temperature - 55 +125 oc operating temperature - 40 +85 oc q1 package (64 - p in vqfn) min. max. units total allowable power dissipation at tamb = 25oc 3500 mw ... derating 35.0 mw/oc storage temperature - 55 +125 oc operating temperature - 40 +85 oc 9.1.2 operating limits correct operation of the device outside thes e limits is not implied. min typ max. units dv dd - dv ss 3.0 3.3 3.6 v dv core - dv ss 1.7 1.8 1.9 v av dd - av ss 3.0 3.3 3.6 v voltage differential between power supplies: dv dd and av dd 0 C ss and av ss 0 C C C C
CMX7163 qam modem CMX7163 ? 9.1.3 operating characteristics details in this section represent design target values and are not currently guaranteed. for the following conditions unless othe rwise specified: external components as recommended in section 5 , external components . maximum load on digital outputs = 30pf. xtal frequency = 9.6mhz ? 0.002% (20ppm); ta mb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v. current consumption figures quoted in this section apply to the device when loaded with fi - 4.x only. current consumption may vary with function image ? . dc parameters notes min. typ. max. u nit supply current (see also section 9.1.4 ) 11 all powersaved ai dd + di dd 10,15 C C idle mode 12,15 di dd 13 C C dd C C additional current for one auxiliary sy stem clock (output running at 5mhz C sysclkpll active) 15 di dd (dv dd = 3.3v, dv core = 1.8v) C C additional current for one auxiliary system clock (output running at 4.8mhz C sysclkpll not required) 15 di dd (dv dd = 3.3v, dv core = 1.8v) C C additional current for each auxiliary adc 15 di dd (dv dd = 3.3v, dv core = 1.8v) C C additional current for each auxiliary dac 14,15 ai dd (av dd = 3.3v) C C notes: 10 idle mode with v bias disabled. 11 tamb = 25c, not including any current drawn from the device pins by external circuitry. 12 system clocks, auxiliary circuits disabled, but all other digital circuits (including the main clock pll) enabled and v bias enabled. 13 using a 19.2mhz exte rnal clock input, xtal oscillator circuit powered down. 14 a lower current is measured when outputting the smallest possible dc level from an auxdac, a higher current is measured when outputting the largest possible dc value. 15 using a 19.2mhz externa l clock input.
CMX7163 qam modem CMX7163 ? dc parameters (continued) notes min. typ. max. unit xtal/clk 20 input logic 1 C C dd input logic 0 C C dd input current (vin = dv dd ) C C ss ) ? C C c - bus interf ace and logic inputs input logic 1 C C dd input logic 0 C C dd input leakage current (logic 1 or 0) ? C C C c - bus interface and logic outputs output logic 1 (i oh = 2ma) 90% C C dd output logic 0 (i ol = - 5ma) C C dd off state leakage current C v bias 21 output voltage offset wrt av dd /2 (i ol < 1 ? C C dd output impedance C C ? notes: 20 characteristics whe n driving the xtal/clk pin with an external clock source. 21 applies when utilising v bias to provide a reference voltage to other parts of the system. when using v bias as a reference, v bias must be buffered. v bias must always be decoupled with a capacito r, as shown in section 4 pcb layout guidelines and power supply decoupling .
CMX7163 qam modem CMX7163 ? a c parameters notes min. typ. max. unit xtal/clk input 'high' pulse width 3 0 15 C C C C C C ? C C C C ? C C C C sysclk1/2 outputs syspll operating frequency 38 C C C C C C C v bias start - up time (from powersave) C C differential i and q inputs input impedance, enabled 31 10 C ? ? C C dd programmable input gain stage gain (at 0db) 33 ? ? ? ? notes: 30 timing for an external input to the xtal/clock pin. 31 with no external components connected. 32 for each input pin and for av dd = 3.3v, the maximum allowed signal swing is: (3.3 x 0.8) - (3.3 x 0.2) = 2.0v. 33 design value. overall attenuation input to output has a design tolerance of 0db 1.0db.
CMX7163 qam modem CMX7163 ? a c parameters notes min. typ. max. unit modulator i/q outputs (i output, q output) power - up to output stable 40 C i/q output coarse gain attenuators attenuation (at 0db) 42 ? ? ? ? ? C C ? ? C C ? C dd - 0.3 v load resistance 20 C C ? notes: 40 power - up refers to issuing a c - bus command to turn on an output. these limits apply only if v bias is on and stable. at power supply switch - on, the default state is for all blocks, except the xtal and c - bus interface, to be in placed in powersave mode. 41 small signal impedance, at av dd = 3.3v and tamb = 25c. 42 figures relate to attenuator block only. design value. overall attenuation input to output has a design t olerance of 0db 1.0db. 43 for each output pin. with respect to the output driving a 20k ? dd /2. 44 the levels of i/q output fine gain and offset (registers $5d and $5e) should be adjusted so that the output voltage remains between 20% and 80% of av dd on each output pin (when 0db of coarse output gain is used). this will produce the best performance when the device operates with av dd = 3.3v.
CMX7163 qam modem CMX7163 ? a c parameters (cont.) notes min. typ. max. unit auxiliary signal inputs (auxadc1 - 4) s ource output impedance 50 C C ? auxiliary 10 - bit adcs resolution C C C C C C ? C C C C C C C C auxiliary 10 - bit dacs resolution C C C C C C ? C C C C notes: 50 denotes output impedance of the driver of the auxiliary input signal, to ensure < 1 bit additional error under nominal c onditions. 51 typical C
CMX7163 qam modem CMX7163 ? 9.1.4 CMX7163 fi - 4.x parametric performance details in this section represent design target values and are not currently guaranteed. for the following conditions unless otherwise specified: external components as recommended in section 5 . maximum load on digital outputs = 30pf. clock source = 19.2mhz ? 0.002% (20ppm) clock input; tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v. reference signal level = 308mv rms at 1khz with av dd = 3.3v signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db, output stage attenuation = 0db. all figures quoted in this section apply to the device when loaded with fi - 4.x only. the use of other function images ? , can modify the parametric performance of the device. dc parameters notes min. typ. max. unit supply current rx mode di dd (9600symbols/s C C C dd (18000symbols/s C C C dd (9600symbols/s C C C dd (18000symbols/s C C C dd (av dd = 3.3v) C C tx mode 61 di dd (9600 symbols/s) C C dd (18000 symbols/s) C C d d (av dd = 3.3v) C C notes: 60 a lower current is measured when searching for framesync1, a higher current is measured when doing automatic modulation detection. 61 transmitting continuous 16 - qam prbs, all gpios and ramdac set to manual.
CMX7163 qam modem CMX7163 ? a c parameters notes min. typ. max. unit modem symbol rate 2000 20000 sym s - 1 modulation qam filter rrc alpha 76 0.2 or 0.35 tx bit - rate accuracy 70 - ppm tx output level (i output, q output) 71 tbd vp - p tx adjacent channel power (i ou tput, q output, prbs) 72 - - - db rx frequency error tolerated 75 +/ - 1.0 khz rx co - channel rejection 73 - - - db rx adjacent channel rejection 73 - - - db notes: 70 determined by the accuracy of the xtal oscillator provided. 71 transmi tting continuous default preamble. 72 see section 8.5 CMX7163 fi - 4.x typical transmit performance 73 see section 8.6 CMX7163 fi - 4.x typical receive performance 75 optimum performance is achieved with 0hz frequency error. the figure quoted is for a symbol rate of 18ksymbols/s . the frequency error tolerated is proportional to t he symbol rate. 76 a user programmable filter option is also provided, allowing for compensation for external hardware and different ?
CMX7163 qam modem CMX7163 ? 9.2 c - bus timing figure 53 c - bus timing c - bus timing notes m in. typ. max. unit t cse csn enable to sclk high time 100 C C ns t csh last sclk high to csn high time 100 C C ns t loz sclk low to rdata output enable time 0.0 C C ns t hiz csn high to rdata high impedance C C 1.0 s t csoff csn high time between tran sactions 1.0 C C s t nxt inter - byte time 100 C C ns t ck sclk cycle time 100 C C ns t ch sclk high time 50 C C ns t cl sclk low time 50 C C ns t cds cdata set - up time 75 C C ns t cdh cdata hold time 25 C C ns t rds rdata set - up time 50 C C ns t rd h rdata hold time 0 C C ns notes: 1. depending on the command, 1 or 2 bytes of cdata are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. rdata is read from the peripheral msb (bit 7) first, lsb (bit 0) last. 2. data is clocke d into the peripheral on the rising sclk edge. 3. commands are acted upon between the last rising edge of sclk of each command and the rising edge of the csn signal. 4. to allow for differing c serial interface formats c - bus compatible ics are able to w ork with sclk pulses starting and ending at either polarity. 5. maximum 30pf load on irqn pin and each c - bus interface line. these timings are for the latest version of c - bus and allow faster transfers than the original c - bus timing specification. the CMX7163 can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints.
CMX7163 qam modem CMX7163 ? 9.3 packaging figure 54 mechanical outline of 64 - pin vqfn (q1) order as part no. CMX7163q1 figure 55 mechanical outline of 64 - pin lqfp (l9) order as part no. CMX7163l9 as package dimensions may change after publication of this datasheet, it is recommended that you check for the latest pa ckaging information from the datasheets page of the cml website: [www.cmlmicro.com].
CMX7163 qam modem CMX7163 ? about firmasic ? cmls proprietary firmasic ? component technology reduces cost, time to market and development risk, with increased flexibili ty for the designer and end application. firmasic ? combines analogue, digital, firmware and memory technologies in a single silicon platform that can be focused to deliver the right feature mix, performance and price for a target application family. spec ific functions of a firmasic ? device are determined by uploading its function image? during device initialization. new function images? may be later provided to supplement and enhance device functions, expanding or modifying end - product features without the need for expensive and time - consuming design changes. firmasic ? devices provide significant time to market and commercial benefits over custom asic, structured asic, fpga and dsp solutions. they may also be exclusively customised where security or int ellectual property issues prevent the use of application specific standard products (assps). handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discha rge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed.

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